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SN74ACT373DBLE

更新时间: 2024-09-09 05:17:59
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德州仪器 - TI 锁存器逻辑集成电路光电二极管输出元件驱动
页数 文件大小 规格书
19页 583K
描述
OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS

SN74ACT373DBLE 数据手册

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SN54ACT373, SN74ACT373  
OCTAL D-TYPE TRANSPARENT LATCHES  
WITH 3-STATE OUTPUTS  
SCAS544E – OCTOBER 1995 – REVISED OCTOBER 2002  
SN54ACT373 . . . J OR W PACKAGE  
SN74ACT373 . . . DB, DW, N, NS, OR PW PACKAGE  
(TOP VIEW)  
4.5-V to 5.5-V V  
Operation  
CC  
Inputs Accept Voltages to 5.5 V  
Max t of 10 ns at 5 V  
pd  
Inputs Are TTL-Voltage Compatible  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
OE  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
CC  
8Q  
8D  
7D  
7Q  
6Q  
6D  
5D  
5Q  
LE  
description/ordering information  
These 8-bit latches feature 3-state outputs  
designed specifically for driving highly capacitive  
or relatively low-impedance loads. The devices  
are particularly suitable for implementing buffer  
registers, I/O ports, bidirectional bus drivers, and  
working registers.  
GND  
The eight latches are D-type transparent latches.  
When the latch-enable (LE) input is high, the Q  
outputs follow the data (D) inputs. When LE is  
taken low, the Q outputs are latched at the logic  
levels set up at the D inputs.  
SN54ACT373 . . . FK PACKAGE  
(TOP VIEW)  
A buffered output-enable (OE) input can be used  
to place the eight outputs in either a normal logic  
state (high or low logic levels) or the  
high-impedance state. In the high-impedance  
state, the outputs neither load nor drive the bus  
lines significantly. The high-impedance state and  
increased drive provide the capability to drive bus  
lines in bus-organized systems without need for  
interface or pullup components.  
3
2
1
20 19  
18  
8D  
7D  
7Q  
6Q  
6D  
2D  
2Q  
3Q  
3D  
4D  
4
5
6
7
8
17  
16  
15  
14  
9 10 11 12 13  
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP – N  
Tube  
SN74ACT373N  
SN74ACT373N  
Tube  
SN74ACT373DW  
SN74ACT373DWR  
SN74ACT373NSR  
SN74ACT373DBR  
SN74ACT373PWR  
SNJ54ACT373J  
SOIC – DW  
ACT373  
Tape and reel  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
–40°C to 85°C  
SOP – NS  
SSOP – DB  
TSSOP – PW  
CDIP – J  
ACT373  
AD373  
AD373  
SNJ54ACT373J  
SNJ54ACT373W  
SNJ54ACT373FK  
–55°C to 125°C  
CFP – W  
Tube  
SNJ54ACT373W  
SNJ54ACT373FK  
LCCC – FK  
Tube  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2002, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74ACT373DBLE 替代型号

型号 品牌 替代类型 描述 数据表
SN74ACT373DBRG4 TI

完全替代

OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
SN74ACT373DBRE4 TI

完全替代

OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
SN74ACT373DBR TI

完全替代

OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS

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SN74ACT373DWG4 TI

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SN74ACT373DWR TI

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SN74ACT373DWRE4 TI

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SN74ACT373DWRG4 TI

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OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
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