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SN74ACT16374-EP

更新时间： 2024-09-17 02:58:39
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德州仪器 - TI 输出元件
页数 文件大小 规格书
8页 133K
描述
16-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOP WITH 3-STATE OUTPUTS

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中文翻译

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SN74ACT16374-EP 数据手册

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SN74ACT16374Q-EP  
16-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOP  
WITH 3-STATE OUTPUTS  
SCAS679B – MAY 2002 – REVISED JULY 2002  
DL PACKAGE  
(TOP VIEW)  
Controlled Baseline  
– One Assembly/Test Site, One Fabrication  
Site  
1OE  
1Q1  
1Q2  
GND  
1Q3  
1Q4  
1
48 1CLK  
47 1D1  
46 1D2  
Extended Temperature Performance of  
–40°C to 125°C  
2
3
Enhanced Diminishing Manufacturing  
Sources (DMS) Support  
GND  
44 1D3  
4
45  
5
Enhanced Product Change Notification  
1D4  
6
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
†
Qualification Pedigree  
V
V
7
CC  
CC  
1Q5  
1Q6  
GND  
1Q7  
1Q8  
2Q1  
2Q2  
GND  
2Q3  
2Q4  
1D5  
1D6  
GND  
1D7  
1D8  
2D1  
2D2  
GND  
2D3  
2D4  
8
Member of the Texas Instruments  
Widebus Family  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
Inputs Are TTL-Voltage Compatible  
3-State Bus Driving True Outputs  
Flow-Through Architecture Optimizes  
PCB Layout  
Distributed V  
and GND Pins Minimize  
High-Speed Switching Noise  
CC  
†
Component qualification in accordance with JEDEC and industry  
standards to ensure reliable operation over an extended  
temperature range. This includes, but is not limited to, highly  
accelerated stress test (HAST) or biased 85/85, temperature  
cycle, autoclave or unbiased HAST, electromigration, bond  
intermetallic life, and mold compound life.  
V
V
CC  
CC  
2Q5  
2Q6  
GND  
2Q7  
2Q8  
2OE  
2D5  
2D6  
GND  
2D7  
2D8  
2CLK  
description  
The  
SN74ACT16374Q-EP  
is  
a
16-bit  
edge-triggered D-type flip-flop with 3-state  
outputs, designed specifically for driving highly  
capacitive or relatively low-impedance loads. It is  
particularly suitable for implementing buffer  
registers, I/O ports, bidirectional bus drivers, and  
working registers.  
This device can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK)  
input, the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs.  
An output-enable (OE) input can be used to place the outputs in either a normal logic state (high or low logic  
levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines  
significantly. The high-impedance state provides the capability to drive bus lines in a bus-organized system,  
without need for interface or pullup components. OE does not affect the internal operations of the flip-flop. Old  
data can be retained or new data can be entered while the outputs are in the high-impedance state.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
‡
T
A
PACKAGE  
–40°C to 125°C  
SSOP – DL Tape and reel  
SN74ACT16374QDLREP  
ACT16374QEP  
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
Copyright 2002, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
12345678

中文翻译

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SN74ACT16374-EP 替代型号

型号 品牌 替代类型 描述 数据表
SN54ACT16374 TI

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