Datasheet > SN74ACT2227

SN74ACT2227

更新时间： 2024-11-08 23:03:11

品牌	Logo	应用领域
德州仪器 - TI		/
页数	文件大小	规格书
13页	176K
描述
DUAL 64 】 1, DUAL 256 】 1 FIRST-IN, FIRST-OUT MEMORIES

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SN74ACT2227 数据手册

SN74ACT2227, SN74ACT2229

DUAL 64 × 1, DUAL 256 × 1

FIRST-IN, FIRST-OUT MEMORIES

SCAS220C – JUNE 1992 – REVISED OCTOBER 1997

DW PACKAGE

(TOP VIEW)

Dual Independent FIFOs Organized as:

64 Words by 1 Bit Each – SN74ACT2227

256 Words by 1 Bit Each – SN74ACT2229

1HF

1AF/AE

1WRTCLK

1WRTEN

1IR

1OE

1RDCLK

Free-Running Read and Write Clocks Can

Be Asynchronous or Coincident on Each

FIFO

26 1RDEN

25 1OR

24 1Q

Input-Ready Flags Synchronized to Write

Clocks

GND

2RESET

Output-Ready Flags Synchronized to Read

Clocks

1RESET

2IR

2WRTEN

2WRTCLK

2AF/AE

2HF

Half-Full and Almost-Full/Almost-Empty

Flags

2OR

Support Clock Frequencies up to 60 MHz

Access Times of 9 ns

2RDEN

2RDCLK

2OE

3-State Data Outputs

Low-Power Advanced CMOS Technology

Packaged in 28-Pin SOIC Package

description

The SN74ACT2227 and SN74ACT2229 are dual FIFOs suited for a wide range of serial-data buffering

applicationsincluding elastic stores for frequencies up to OC-1 telecommunication rates. Each FIFO on the chip

is arranged as 64 × 1 (SN74ACT2227) or 256 × 1 (SN74ACT2229) and has control signals and status flags for

independent operation. Output flags for each FIFO include input ready (1IR or 2IR), output ready (1OR or 2OR),

half full (1HF or 2HF), and almost full/almost empty (1AF/AE or 2AF/AE).

Serial data is written into a FIFO on the low-to-high transition of the write-clock (1WRTCLK or 2WRTCLK) input

when the write-enable (1WRTEN or 2WRTEN) input and input-ready flag (1IR or 2IR) output are both high.

Serial data is read from a FIFO on the low-to-high transition of the read-clock (1RDCLK or 2RDCLK) input when

the read-enable (1RDEN or 2RDEN) input and output-ready flag (1OR or 2OR) output are both high. The read

and write clocks of a FIFO can be asynchronous to one another. A FIFO data output (1Q or 2Q) is in the

high-impedance state when its output-enable (1OE or 2OE) input is low.

Each input-ready flag (1IR or 2IR) is synchronized by two flip-flop stages to its write clock (1WRTCLK or

2WRTCLK), and each output-ready flag (1OR or 2OR) is synchronized by three flip-flop stages to its read clock

(1RDCLK or 2RDCLK). This multistage synchronization ensures reliable flag-output states when data is written

and read asynchronously.

A half-full flag (1HF or 2HF) is high when the number of bits stored in its FIFO is greater than or equal to half

the depth of the FIFO. An almost-full/almost-empty flag (1AF/AE or 2AF/AE) is high when eight or fewer bits

are stored in its FIFO and when eight or fewer empty locations are left in the FIFO. A bit present on the data

output is not stored in the FIFO.

The SN74ACT2227 and SN74ACT2229 are characterized for operation from –40°C to 85°C.

For more information on this device family, see the application report FIFOs With a Word Width of One Bit

(literature number SCAA006).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...13

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与SN74ACT2227相关器件

型号	品牌	获取价格	描述	数据表
SN74ACT2227_15	TI	获取价格	DUAL 64 Ã 1, DUAL 256 Ã 1 FIRST-IN, FIRST-O
SN74ACT2227DW	TI	获取价格	DUAL 64 】 1, DUAL 256 】 1 FIRST-IN, FIRST-OUT
SN74ACT2228	TI	获取价格	DUAL 64 】 1, DUAL 256 】 1 CLOCKED FIRST-IN, F
SN74ACT2228DW	TI	获取价格	DUAL 64 】 1, DUAL 256 】 1 CLOCKED FIRST-IN, F
SN74ACT2228DWR	TI	获取价格	DUAL 64 】 1, DUAL 256 】 1 CLOCKED FIRST-IN, F
SN74ACT2229	TI	获取价格	DUAL 64 】 1, DUAL 256 】 1 FIRST-IN, FIRST-OUT
SN74ACT2229DW	TI	获取价格	DUAL 64 】 1, DUAL 256 】 1 FIRST-IN, FIRST-OUT
SN74ACT2229DWR	TI	获取价格	256 x 1 x 2 dual independent synchronous FIFO memories 28-SOIC -40 to 85
SN74ACT2235	TI	获取价格	1024 】 9 】 2 ASYNCHRONOUS BIDIRECTIONAL FIRST
SN74ACT2235-20FN	TI	获取价格	1024 】 9 】 2 ASYNCHRONOUS BIDIRECTIONAL FIRST

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