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SN54LVTH241 PDF预览

SN54LVTH241

更新时间： 2024-11-19 23:03:07
品牌 Logo 应用领域
德州仪器 - TI 驱动器输出元件
页数 文件大小 规格书
12页 309K
描述
3.3-V ABT OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

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SN54LVTH241 数据手册

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SCAS352K − MARCH 1994 − REVISED OCTOBER 2003  
SN54LVTH241 . . . J OR W PACKAGE  
SN74LVTH241 . . . DB, DW, NS, OR PW PACKAGE  
(TOP VIEW)  
D
D
D
D
D
Support Mixed-Mode Signal Operation (5-V  
Input and Output Voltages With 3.3-V V  
)
CC  
Support Unregulated Battery Operation  
Down to 2.7 V  
1OE  
1A1  
2Y4  
1A2  
2Y3  
1A3  
2Y2  
1A4  
2Y1  
GND  
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
2OE  
1Y1  
2A4  
1Y2  
2A3  
1Y3  
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
CC  
= 3.3 V, T = 25°C  
A
I
and Power-Up 3-State Support Hot  
off  
Insertion  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
13 2A2  
12 1Y4  
D
D
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
11  
2A1  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
SN54LVTH241 . . . FK PACKAGE  
(TOP VIEW)  
description/ordering information  
3
2 1 20 19  
18  
These octal buffers/drivers are designed  
1A2  
2Y3  
1A3  
2Y2  
1A4  
1Y1  
2A4  
1Y2  
2A3  
1Y3  
4
5
6
7
8
specifically for low-voltage (3.3-V) V  
operation,  
17  
16  
15  
14  
CC  
with the capability to provide a TTL interface to a  
5-V system environment.  
The ’LVTH241 devices are organized as two 4-bit  
line drivers with separate output-enable (1OE,  
2OE) inputs. When 1OE is low or 2OE is high, the  
devices pass noninverted data from the A inputs  
to the Y outputs. When 1OE is high or 2OE is low,  
the outputs are in the high-impedance state.  
9 10 11 12 13  
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors  
with the bus-hold circuitry is not recommended.  
ORDERING INFORMATION  
ORDERABLE  
†
T
PACKAGE  
TOP-SIDE MARKING  
A
PART NUMBER  
SN74LVTH241DW  
SN74LVTH241DWR  
SN74LVTH241NSR  
SN74LVTH241DBR  
SN74LVTH241PW  
SN74LVTH241PWR  
SNJ54LVTH241J  
Tube  
SOIC − DW  
LVTH241  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SOP − NS  
LVTH241  
LXH241  
−40°C to 85°C  
SSOP − DB  
TSSOP − PW  
LXH241  
Tape and reel  
Tube  
CDIP − J  
CFP − W  
LCCC − FK  
SNJ54LVTH241J  
SNJ54LVTH241W  
SNJ54LVTH241FK  
Tube  
SNJ54LVTH241W  
SNJ54LVTH241FK  
−55°C to 125°C  
Tube  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...12

中文翻译

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