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SN54LVTH245AJ

更新时间： 2024-11-19 23:03:07
品牌 Logo 应用领域
德州仪器 - TI 总线收发器输出元件
页数 文件大小 规格书
7页 97K
描述
3.3-V ABT OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

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SN54LVTH245AJ 数据手册

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SN54LVTH245A, SN74LVTH245A  
3.3-V ABT OCTAL BUS TRANSCEIVERS  
WITH 3-STATE OUTPUTS  
SCBS130P – MAY 1992 – REVISED APRIL 1999  
SN54LVTH245A . . . J OR W PACKAGE  
SN74LVTH245A . . . DB, DW, OR PW PACKAGE  
(TOP VIEW)  
State-of-the-Art Advanced BiCMOS  
Technology (ABT) Design for 3.3-V  
Operation and Low Static-Power  
Dissipation  
DIR  
A1  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
V
CC  
Support Mixed-Mode Signal Operation (5-V  
Input and Output Voltages With 3.3-V V  
OE  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
)
CC  
A2  
Support Unregulated Battery Operation  
Down to 2.7 V  
A3  
A4  
A5  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
A6  
= 3.3 V, T = 25°C  
CC  
A
A7  
I
and Power-Up 3-State Support Hot  
off  
A8  
Insertion  
GND  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
SN54LVTH245A . . . FK PACKAGE  
(TOP VIEW)  
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
3
2
1 20 19  
18  
A3  
A4  
A5  
A6  
A7  
4
5
6
7
8
B1  
B2  
B3  
B4  
B5  
17  
16  
15  
14  
Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages, Ceramic Chip Carriers (FK),  
Ceramic Flat (W) Packages, and Ceramic  
(J) DIPs  
9 10 11 12 13  
description  
These octal bus transceivers are designed specifically for low-voltage (3.3-V) V  
capability to provide a TTL interface to a 5-V system environment.  
operation, but with the  
CC  
These devices are designed for asynchronous communication between data buses. They transmit data from  
the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR)  
input. The output-enable (OE) input can be used to disable the devices so the buses are effectively isolated.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
When V is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.  
CC  
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V  
through a pullup resistor;  
CC  
the minimum value of the resistor is determined by the current-sinking capability of the driver.  
These devices are fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry  
off  
off  
disables the outputs, preventing damaging current backflow through the devices when they are powered down.  
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,  
which prevents driver conflict.  
The SN54LVTH245A is characterized for operation over the full military temperature range of –55°C to 125°C.  
The SN74LVTH245A is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1999, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567

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