SN54LVT543, SN74LVT543
3.3-V ABT OCTAL REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS137D – MAY 1992 – REVISED JULY 1995
SN54LVT543 . . . JT PACKAGE
SN74LVT543 . . . DB, DW, OR PW PACKAGE
(TOP VIEW)
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static Power
Dissipation
LEBA
OEBA
A1
1
2
3
4
5
6
7
8
9
10
24
V
CC
Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V V
23 CEBA
22 B1
21 B2
20 B3
19 B4
18 B5
17 B6
16 B7
)
CC
A2
A3
A4
A5
A6
A7
A8
Support Unregulated Battery Operation
Down to 2.7 V
Typical V
< 0.8 V at V
(Output Ground Bounce)
OLP
= 3.3 V, T = 25°C
CC
A
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)
15
B8
CEAB 11
GND 12
14 LEAB
13 OEAB
Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17
SN54LVT543 . . . FK PACKAGE
(TOP VIEW)
Bus-Hold Data Inputs Eliminate the Need
for External Pullup Resistors
Support Live Insertion
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK), and
Ceramic (JT) DIPs
4
3
2
1
28 27 26
25
A2
A3
A4
NC
A5
A6
A7
B2
B3
B4
5
24
23
6
7
22 NC
21 B5
20 B6
19 B7
8
description
9
10
11
Theseoctaltransceiversaredesignedspecifically
for low-voltage (3.3-V) V operation, but with the
CC
12 13 14 15 16 17 18
capability to provide a TTL interface to a 5-V
system environment.
The ’LVT543 contain two sets of D-type latches for
temporary storage of data flowing in either
direction. Separate latch-enable (LEAB or LEBA)
and output-enable (OEAB or OEBA) inputs are
provided for each register to permit independent
control in either direction of data flow.
NC – No internal connection
The A-to-B enable (CEAB) input must be low in order to enter data from A or to output data from B. If CEAB
is low and LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts
the A latches in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect
the data present at the output of the A latches. Data flow from B to A is similar but requires using the CEBA,
LEBA, and OEBA inputs.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1995, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
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