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SN54LVT16500 PDF预览

SN54LVT16500

更新时间： 2024-02-27 16:23:29
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德州仪器 - TI 输出元件
页数 文件大小 规格书
9页 154K
描述
3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

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SN54LVT16500 数据手册

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SN54LVT16500, SN74LVT16500  
3.3-V ABT 18-BIT UNIVERSAL BUS TRANSCEIVERS  
WITH 3-STATE OUTPUTS  
SCBS146D – MAY 1992 – REVISED NOVEMBER 1996  
SN54LVT16500 . . . WD PACKAGE  
SN74LVT16500 . . . DGG OR DL PACKAGE  
(TOP VIEW)  
State-of-the-Art Advanced BiCMOS  
Technology (ABT) Design for 3.3-V  
Operation and Low-Static Power  
Dissipation  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
OEAB  
LEAB  
A1  
GND  
CLKAB  
B1  
Members of the Texas Instruments  
Widebus Family  
2
3
Support Mixed-Mode Signal Operation (5-V  
Input and Output Voltages With 3.3-V V  
4
GND  
A2  
GND  
B2  
)
5
CC  
6
A3  
B3  
Support Unregulated Battery Operation  
Down to 2.7 V  
7
V
V
CC  
CC  
8
A4  
B4  
UBT (Universal Bus Transceiver)  
Combines D-Type Latches and D-Type  
Flip-Flops for Operation in Transparent,  
Latched, or Clocked Mode  
9
A5  
B5  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
A6  
GND  
A7  
A8  
A9  
A10  
A11  
A12  
GND  
A13  
A14  
A15  
B6  
GND  
B7  
B8  
B9  
B10  
B11  
B12  
GND  
B13  
B14  
B15  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
= 3.3 V, T = 25°C  
CC  
A
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model  
(C = 200 pF, R = 0)  
Latch-Up Performance Exceeds 500 mA  
Per JEDEC Standard JESD-17  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
V
V
CC  
A16  
CC  
B16  
B17  
GND  
B18  
CLKBA  
GND  
A17  
GND  
A18  
OEBA  
LEBA  
Support Live Insertion  
Distributed V  
Minimizes High-Speed Switching Noise  
and GND Pin Configuration  
CC  
Flow-Through Architecture Optimizes  
PCB Layout  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages and 380-mil  
Fine-Pitch Ceramic Flat (WD) Package  
Using 25-mil Center-to-Center Spacings  
description  
The ’LVT16500 are 18-bit universal bus transceivers designed for low-voltage (3.3-V) V  
the capability to provide a TTL interface to a 5-V system environment.  
operation, but with  
CC  
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),  
and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when  
LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is  
low, the A-bus data is stored in the latch/flip-flop on the high-to-low transition of CLKAB. Output-enable OEAB  
is active high. When OEAB is high, the B-port outputs are active. When OEAB is low, the B-port outputs are in  
the high-impedance state.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus and UBT are trademarks of Texas Instruments Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

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