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SN54LVT16952WD PDF预览

SN54LVT16952WD

更新时间： 2024-01-17 15:24:24
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德州仪器 - TI 输出元件
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11页 192K
描述
3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

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SN54LVT16952WD 数据手册

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SN54LVT16952, SN74LVT16952  
3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS  
WITH 3-STATE OUTPUTS  
SCBS151D – MAY 1992 – REVISED AUGUST 1996  
SN54LVT16952 . . . WD PACKAGE  
SN74LVT16952 . . . DGG OR DL PACKAGE  
(TOP VIEW)  
State-of-the-Art Advanced BiCMOS  
Technology (ABT) Design for 3.3-V  
Operation and Low-Static Power  
Dissipation  
1OEAB  
1CLKAB  
1CLKENAB  
GND  
1
2
3
4
5
6
7
8
9
56 1OEBA  
55 1CLKBA  
54 1CLKENBA  
53 GND  
Members of the Texas Instruments  
Widebus Family  
Support Mixed-Mode Signal Operation (5-V  
Input and Output Voltages With 3.3-V V  
)
CC  
1A1  
1A2  
52 1B1  
Support Unregulated Battery Operation  
Down to 2.7 V  
51 1B2  
V
50  
V
CC  
CC  
1A3  
1A4  
49 1B3  
48 1B4  
47 1B5  
46 GND  
45 1B6  
44 1B7  
43 1B8  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
= 3.3 V, T = 25°C  
CC  
A
1A5 10  
GND 11  
1A6 12  
1A7 13  
1A8 14  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model  
(C = 200 pF, R = 0)  
Latch-Up Performance Exceeds 500 mA  
Per JEDEC Standard JESD-17  
15  
42  
2A1  
2B1  
2A2 16  
2A3 17  
41 2B2  
40 2B3  
Bus-Hold Data Inputs Eliminate the Need  
for External Pullup Resistors  
18  
19  
39  
38  
GND  
2A4  
GND  
2B4  
Support Live Insertion  
Distributed V  
Minimizes High-Speed Switching Noise  
and GND Pin Configuration  
2A5 20  
37 2B5  
CC  
21  
22  
23  
24  
25  
26  
27  
28  
36  
35  
34  
33  
32  
31  
30  
29  
2A6  
2B6  
V
V
Flow-Through Architecture Optimizes  
PCB Layout  
CC  
CC  
2A7  
2A8  
GND  
2B7  
2B8  
GND  
2CLKENBA  
2CLKBA  
2OEBA  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages and 380-mil  
Fine-Pitch Ceramic Flat (WD) Package  
Using 25-mil Center-to-Center Spacings  
2CLKENAB  
2CLKAB  
2OEAB  
description  
The ’LVT16952 are 16-bit registered transceivers designed for low-voltage (3.3-V) V  
operation, but with the  
CC  
capability to provide a TTL interface to a 5-V system environment. These devices can be used as two 8-bit  
transceivers or one 16-bit transceiver. Data on the A or B bus is stored in the registers on the low-to-high  
transition of the clock (CLKAB or CLKBA) input provided that the clock-enable (CLKENAB or CLKENBA) input  
is low. Taking the output-enable (OEAB or OEBA) input low accesses the data on either port.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
The SN74LVT16952 is available in TI’s shrink small-outline (DL) and thin shrink small-outline (DGG) packages,  
which provide twice the I/O pin count and functionality of standard small-outline packages in the same  
printed-circuit-board area.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...11

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