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SN54LVT245 PDF预览

SN54LVT245

更新时间: 2024-01-13 22:20:42
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德州仪器 - TI 总线收发器输出元件
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描述
3.3-V ABT OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

SN54LVT245 数据手册

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SN54LVT245B, SN74LVT245B  
3.3-V ABT OCTAL BUS TRANSCEIVERS  
WITH 3-STATE OUTPUTS  
SCES004D – JANUARY 1995 – REVISED APRIL 2000  
SN54LVT245B . . . J OR W PACKAGE  
SN74LVT245B . . . DB, DW, OR PW PACKAGE  
(TOP VIEW)  
State-of-the-Art Advanced BiCMOS  
Technology (ABT) Design for 3.3-V  
Operation and Low Static-Power  
Dissipation  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
DIR  
A1  
V
CC  
Support Mixed-Mode Signal Operation (5-V  
Input and Output Voltages With 3.3-V V  
OE  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
)
CC  
A2  
Support Unregulated Battery Operation  
Down to 2.7 V  
A3  
A4  
A5  
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
CC  
= 3.3 V, T = 25°C  
A6  
A
A7  
I
and Power-Up 3-State Support Hot  
off  
A8  
Insertion  
GND  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
SN54LVT245B . . . FK PACKAGE  
(TOP VIEW)  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
– 1000-V Charged-Device Model (C101)  
Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages, Ceramic Chip Carriers (FK),  
Ceramic Flat (W) Packages, and Ceramic  
(J) DIPs  
3
2
1 20 19  
18  
B1  
B2  
A3  
A4  
A5  
A6  
A7  
4
5
6
7
8
17  
16 B3  
15  
14  
B4  
B5  
9 10 11 12 13  
description  
These octal bus transceivers are designed  
specifically for low-voltage (3.3-V) V operation,  
CC  
but with the capability to provide a TTL interface  
to a 5-V system environment.  
These devices are designed for asynchronous communication between data buses. They transmit data from  
the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR)  
input. The output-enable (OE) input can be used to disable the devices so the buses are effectively isolated.  
When V  
is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.  
CC  
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V  
the minimum value of the resistor is determined by the current-sinking capability of the driver.  
through a pullup resistor;  
CC  
These devices are fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry  
off  
off  
disables the outputs, preventing damaging current backflow through the devices when they are powered down.  
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,  
which prevents driver conflict.  
The SN54LVT245B is characterized for operation over the full military temperature range of –55°C to 125°C.  
The SN74LVT245B is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2000, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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