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SN54LVT18502HV PDF预览

SN54LVT18502HV

更新时间： 2024-11-26 22:36:43
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路测试输出元件信息通信管理
页数 文件大小 规格书
29页 405K
描述
3.3-V ABT SCAN TEST DEVICE WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

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中文翻译

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SN54LVT18502HV 技术参数

生命周期：Obsolete零件包装代码：QFP
包装说明：QFF,针数：68
Reach Compliance Code：unknown风险等级：5.56
Is Samacsys：N其他特性：WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION
系列：LVTJESD-30 代码：S-GQFP-F68
长度：12.51 mm负载电容（CL）：50 pF
逻辑集成电路类型：BOUNDARY SCAN REG BUS TRANSCEIVER位数：9
功能数量：2端口数量：2
端子数量：68最高工作温度：125 °C
最低工作温度：-55 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：CERAMIC, GLASS-SEALED
封装代码：QFF封装形状：SQUARE
封装形式：FLATPACK最大电源电流（ICC）：30 mA
传播延迟（tpd）：8.5 ns认证状态：Not Qualified
座面最大高度：3.86 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：BICMOS
温度等级：MILITARY端子形式：FLAT
端子节距：0.635 mm端子位置：QUAD
宽度：12.51 mmBase Number Matches：1

SN54LVT18502HV 数据手册

 浏览型号SN54LVT18502HV的Datasheet PDF文件第2页浏览型号SN54LVT18502HV的Datasheet PDF文件第3页浏览型号SN54LVT18502HV的Datasheet PDF文件第4页浏览型号SN54LVT18502HV的Datasheet PDF文件第5页浏览型号SN54LVT18502HV的Datasheet PDF文件第6页浏览型号SN54LVT18502HV的Datasheet PDF文件第7页 
SN54LVT18502  
3.3-V ABT SCAN TEST DEVICE  
WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS  
SCBS669 – JULY 1996  
Member of the Texas Instruments SCOPE  
Family of Testability Products  
Compatible With the IEEE Standard  
1149.1-1990 (JTAG) Test Access Port and  
Boundary-Scan Architecture  
Member of the Texas Instruments  
Widebus Family  
SCOPE Instruction Set  
– IEEE Standard 1149.1-1990 Required  
Instructions and Optional CLAMP and  
HIGHZ  
– Parallel-Signature Analysis at Inputs  
– Pseudo-Random Pattern Generation  
From Outputs  
State-of-the-Art 3.3-V ABT Design Supports  
Mixed-Mode Signal Operation (5-V Input  
and Output Voltages With 3.3-V V  
)
CC  
Supports Unregulated Battery Operation  
Down to 2.7 V  
UBT (Universal Bus Transceiver)  
Combines D-Type Latches and D-Type  
Flip-Flops for Operation in Transparent,  
Latched, or Clocked Mode  
– Sample Inputs/Toggle Outputs  
– Binary Count From Outputs  
– Device Identification  
– Even-Parity Opcodes  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup Resistors  
Packaged in 68-Pin Ceramic Quad Flat (HV)  
Packages Using 25-mil Center-to-Center  
Spacings  
HV PACKAGE  
(TOP VIEW)  
9
8
7
6
5
4
3
2 1 68 67 66 65 64 63 62 61  
1A3  
1A4  
1A5  
GND  
1A6  
1A7  
1A8  
1A9  
NC  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
60 1B4  
59 1B5  
58 1B6  
57 GND  
56 1B7  
55 1B8  
54 1B9  
53  
V
CC  
52 NC  
51 2B1  
50 2B2  
49 2B3  
48 2B4  
47 GND  
46 2B5  
45 2B6  
44 2B7  
V
CC  
2A1  
2A2  
2A3  
GND  
2A4  
2A5  
2A6  
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43  
NC – No internal connection  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
SCOPE, Widebus, and UBT are trademarks of Texas Instruments Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...29

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