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SN54LVT240A PDF预览

SN54LVT240A

更新时间： 2024-11-03 23:03:07
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德州仪器 - TI 驱动器输出元件
页数 文件大小 规格书
7页 112K
描述
3.3-V ABT OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

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SN54LVT240A 数据手册

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SN54LVT240A, SN74LVT240A  
3.3-V ABT OCTAL BUFFERS/DRIVERS  
WITH 3-STATE OUTPUTS  
SCBS134I – SEPTEMBER 1992 – REVISED APRIL 2000  
SN54LVT240A . . . J PACKAGE  
SN74LVT240A . . . DB, DW, OR PW PACKAGE  
(TOP VIEW)  
State-of-the-Art Advanced BiCMOS  
Technology (ABT) Design for 3.3-V  
Operation and Low Static-Power  
Dissipation  
1OE  
1A1  
2Y4  
1A2  
2Y3  
1A3  
2Y2  
1A4  
2Y1  
GND  
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
Support Mixed-Mode Signal Operation (5-V  
Input and Output Voltages With 3.3-V V  
2OE  
1Y1  
2A4  
1Y2  
2A3  
1Y3  
)
CC  
Support Unregulated Battery Operation  
Down to 2.7 V  
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
CC  
= 3.3 V, T = 25°C  
A
13 2A2  
12 1Y4  
I
and Power-Up 3-State Support Hot  
off  
Insertion  
11  
2A1  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
SN54LVT240A . . . FK PACKAGE  
(TOP VIEW)  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
– 1000-V Charged-Device Model (C101)  
Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages, Ceramic Chip Carriers (FK), and  
Ceramic (J) DIPs  
3
2
1 20 19  
18  
4
5
6
7
8
1Y1  
2A4  
1Y2  
2A3  
1Y3  
1A2  
2Y3  
1A3  
2Y2  
1A4  
17  
16  
15  
14  
9 10 11 12 13  
description  
These octal buffers and line drivers are designed  
specifically for low-voltage (3.3-V) V operation,  
CC  
but with the capability to provide a TTL interface  
to a 5-V system environment.  
These devices are organized as two 4-bit buffer/line drivers with separate output-enable (OE) inputs. When OE  
is low, the devices pass data from the A inputs to the Y outputs. When OE is high, the outputs are in the  
high-impedance state.  
When V  
is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.  
CC  
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V  
the minimum value of the resistor is determined by the current-sinking capability of the driver.  
through a pullup resistor;  
CC  
These devices are fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry  
off  
off  
disables the outputs, preventing damaging current backflow through the devices when they are powered down.  
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,  
which prevents driver conflict.  
The SN54LVT240A is characterized for operation over the full military temperature range of –55°C to 125°C.  
The SN74LVT240A is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2000, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567

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