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SN54LVT16646

更新时间： 2024-11-03 23:03:07
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德州仪器 - TI 输出元件
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10页 179K
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3.3-V ABT 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

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SN54LVT16646 数据手册

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SN54LVT16646, SN74LVT16646  
3.3-V ABT 16-BIT BUS TRANSCEIVERS  
WITH 3-STATE OUTPUTS  
SCBS149C – JULY 1994 – REVISED JULY 1995  
SN54LVT16646 . . . WD PACKAGE  
SN74LVT16646 . . . DGG OR DL PACKAGE  
(TOP VIEW)  
State-of-the-Art Advanced BiCMOS  
Technology (ABT) Design for 3.3-V  
Operation and Low-Static Power  
Dissipation  
1DIR  
1CLKAB  
1SAB  
GND  
1OE  
1
2
3
4
5
6
7
8
9
56  
55  
54  
53  
52  
51  
50  
49  
48  
Members of the Texas Instruments  
Widebus Family  
1CLKBA  
1SBA  
GND  
1B1  
Support Mixed-Mode Signal Operation (5-V  
Input and Output Voltages With 3.3-V V  
)
1A1  
1A2  
CC  
1B2  
Support Unregulated Battery Operation  
Down to 2.7 V  
V
V
CC  
CC  
1A3  
1A4  
1B3  
1B4  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
= 3.3 V, T = 25°C  
CC  
A
1A5 10  
47 1B5  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883C, Method 3015; Exceeds  
200 V Using Machine Model  
(C = 200 pF, R = 0)  
GND  
1A6  
GND  
1B6  
11  
12  
46  
45  
1A7 13  
1A8 14  
2A1 15  
2A2 16  
2A3 17  
GND 18  
2A4 19  
2A5 20  
2A6 21  
44 1B7  
43 1B8  
42 2B1  
41 2B2  
40 2B3  
39 GND  
38 2B4  
37 2B5  
36 2B6  
Latch-Up Performance Exceeds 500 mA  
Per JEDEC Standard JESD-17  
Bus-Hold Data Inputs Eliminate the Need  
for External Pullup Resistors  
Support Live Insertion  
Distributed V  
Minimizes High-Speed Switching Noise  
and GND Pin Configuration  
CC  
V
22  
35  
V
CC  
CC  
Flow-Through Architecture Optimizes  
PCB Layout  
2A7 23  
34 2B7  
2A8 24  
33 2B8  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages and 380-mil  
Fine-Pitch Ceramic Flat (WD) Package  
Using 25-mil Center-to-Center Spacings  
GND 25  
32 GND  
31 2SBA  
30 2CLKBA  
29 2OE  
2SAB 26  
2CLKAB 27  
2DIR 28  
description  
The ’LVT16646 are 16-bit bus transceivers designed for low-voltage (3.3-V) V  
capability to provide a TTL interface to a 5-V system environment.  
operation, but with the  
CC  
These devices can be used as two 8-bit transceivers or one 16-bit transceiver. Data on the A or B bus is clocked  
into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1  
illustrates the four fundamental bus-management functions that can be performed with the ′LVT16646.  
Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the  
transceiver mode, data present at the high-impedance port may be stored in either register or in both. The  
select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The circuitry  
used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition  
between stored and real-time data. The direction control (DIR) determines which bus receives data when OE  
is low. In the isolation mode (OE high), A data may be stored in one register and/or B data may be stored in the  
other register.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments Incorporated.  
Copyright 1995, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...10

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