SN54LS173A

更新时间： 2024-09-09 23:06:11

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		输出元件
页数	文件大小	规格书
6页	210K
描述
4-BIT D-TYPE REGISTER WITH 3-STATE OUTPUTS

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中文翻译

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数据手册

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SN54LS173A 数据手册

SN54/74LS173A

4-BIT D-TYPE REGISTER

WITH 3-STATE OUTPUTS

The SN54/74LS173A is a high-speed 4-Bit Register featuring 3-state

outputs for use in bus-organized systems. The clock is fully edge-triggered

allowing either a load from the D inputs or a hold (retain register contents)

4-BIT D-TYPE REGISTER

WITH 3-STATE OUTPUTS

depending on the state of the Input Enable Lines (IE , IE ). A HIGH on either

Output Enable line (OE , OE ) brings the output to a high impedance state

LOW POWER SCHOTTKY

without affecting the actual register contents. A HIGH on the Master Reset

(MR) input resets the Register regardless of the state of the Clock (CP), the

Output Enable (OE , OE ) or the Input Enable (IE , IE ) lines.

• Fully Edge-Triggered

• 3-State Outputs

J SUFFIX

CERAMIC

CASE 620-09

• Gated Input and Output Enables

• Input Clamp Diodes Limit High-Speed Termination Effects

CONNECTION DIAGRAM DIP (TOP VIEW)

N SUFFIX

PLASTIC

CASE 648-08

NOTE:

The Flatpak version

has the same pinouts

(Connection Diagram) as

the Dual In-Line Package.

D SUFFIX

SOIC

CASE 751B-03

ORDERING INFORMATION

SN54LSXXXJ

Ceramic

SN74LSXXXN Plastic

SN74LSXXXD SOIC

PIN NAMES

LOADING (Note a)

HIGH

LOW

D –D

Data Inputs

0.5 U.L.

0.25 U.L.

LOGIC SYMBOL

IE –IE

Input Enable (Active LOW)

Output Enable (Active LOW) Inputs

Clock Pulse (Active HIGH Going Edge)

Input

0.5 U.L.

OE –OE

Q –Q

Master Reset Input (Active HIGH)

Outputs (Note b)

0.5 U.L.

65 (25) U.L. 15 (7.5) U.L.

0.25 U.L.

NOTES:

a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.

b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)

b. Temperature Ranges.

FAST AND LS TTL DATA

5-316

12 3 4 5 6

中文翻译

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