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SN54LS175 PDF预览

SN54LS175

更新时间: 2024-09-13 23:06:11
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 触发器
页数 文件大小 规格书
5页 174K
描述
QUAD D FLIP-FLOP

SN54LS175 数据手册

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SN54/74LS175  
QUAD D FLIP-FLOP  
The LSTTL/MSI SN54/74LS175 is a high speed Quad D Flip-Flop. The  
device is useful for general flip-flop requirements where clock and clear inputs  
are common. The information on the D inputs is stored during the LOW to  
HIGH clock transition. Both true and complemented outputs of each flip-flop  
are provided. A Master Reset input resets all flip-flops, independent of the  
Clock or D inputs, when LOW.  
QUAD D FLIP-FLOP  
The LS175 is fabricated with the Schottky barrier diode process for high  
speed and is completely compatible with all Motorola TTL families.  
LOW POWER SCHOTTKY  
Edge-Triggered D-Type Inputs  
Buffered-Positive Edge-Triggered Clock  
Clock to Output Delays of 30 ns  
Asynchronous Common Reset  
True and Complement Output  
Input Clamp Diodes Limit High Speed Termination Effects  
J SUFFIX  
CERAMIC  
CASE 620-09  
CONNECTION DIAGRAM DIP (TOP VIEW)  
16  
1
NOTE:  
N SUFFIX  
PLASTIC  
CASE 648-08  
The Flatpak version  
has the same pinouts  
(Connection Diagram) as  
the Dual In-Line Package.  
16  
1
D SUFFIX  
SOIC  
CASE 751B-03  
PIN NAMES  
LOADING (Note a)  
16  
1
HIGH  
LOW  
D D  
0
Data Inputs  
0.5 U.L.  
0.5 U.L.  
0.5 U.L.  
10 U.L.  
10 U.L.  
0.25 U.L.  
0.25 U.L.  
0.25 U.L.  
5 (2.5) U.L.  
5 (2.5) U.L.  
3
CP  
Clock (Active HIGH Going Edge) Input  
Master Reset (Active LOW) Input  
True Outputs (Note b)  
ORDERING INFORMATION  
MR  
SN54LSXXXJ  
Ceramic  
Q Q  
0
3
3
SN74LSXXXN Plastic  
SN74LSXXXD SOIC  
Q Q  
Complemented Outputs (Note b)  
0
NOTES:  
a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.  
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)  
b. Temperature Ranges.  
LOGIC SYMBOL  
LOGIC DIAGRAM  
FAST AND LS TTL DATA  
5-327  

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