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ꢊ ꢅꢆꢋꢌ ꢍꢎꢏ ꢍ ꢐꢆꢑ ꢒꢏ ꢏꢍ ꢑꢍꢎ ꢎꢐꢆ ꢓꢔ ꢍ ꢕ ꢌꢒ ꢔ ꢐꢕ ꢌꢊ ꢔ
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ꢖ ꢒꢆ ꢄ ꢇ ꢐꢀꢆꢋꢆ ꢍ ꢊ ꢗꢆ ꢔꢗ ꢆ
SCLS005D − MARCH 1984 − REVISED AUGUST 2003
SN54HCT374 . . . J OR W PACKAGE
SN74HCT374 . . . DB, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
D
D
Operating Voltage Range of 4.5 V to 5.5 V
High-Current 3-State True Outputs Can
Drive Up To 15 LSTTL Loads
D
D
D
D
D
D
D
Low Power Consumption, 80-µA Max I
Typical t = 22 ns
pd
6-mA Output Drive at 5 V
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
V
CC
8Q
8D
1
2
3
4
5
6
7
8
9
20
19
18
CC
17 7D
16 7Q
15 6Q
14
Low Input Current of 1 µA Max
Inputs Are TTL-Voltage Compatible
Eight D-Type Flip-Flops in a Single Package
Full Parallel Access for Loading
6D
13 5D
12 5Q
11 CLK
GND 10
description/ordering information
These 8-bit flip-flops feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
SN54HCT374 . . . FK PACKAGE
(TOP VIEW)
3
2
1
20 19
18
8D
7D
7Q
2D
2Q
3Q
3D
4D
4
5
6
7
8
17
16
The eight flip-flops of the ’HCT374 devices are
edge-triggered D-type flip-flops. On the positive
transition of the clock (CLK) input, the Q outputs
are set to the logic levels that were set up at the
data (D) inputs.
15 6Q
14
9 10 11 12 13
6D
An output-enable (OE) input places the eight
outputs in either a normal logic state (high or low
logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP − N
Tube of 20
Tube of 25
Reel of 2000
Reel of 2000
Reel of 2000
Tube of 70
Reel of 2000
Reel of 250
Tube of 20
Tube of 85
Tube of 55
SN74HCT374N
SN74HCT374N
SN74HCT374DW
SN74HCT374DWR
SN74HCT374NSR
SN74HCT374DBR
SN74HCT374PW
SN74HCT374PWR
SN74HCT374PWT
SNJ54HCT374J
SOIC − DW
HCT374
SOP − NS
HCT374
HT374
−40°C to 85°C
SSOP − DB
TSSOP − PW
HT374
CDIP − J
CFP − W
LCCC − FK
SNJ54HCT374J
SNJ54HCT374W
SNJ54HCT374FK
SNJ54HCT374W
SNJ54HCT374FK
−55°C to 125°C
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2003, Texas Instruments Incorporated
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