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SN54HCT541_07

更新时间: 2024-11-05 05:05:03
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德州仪器 - TI 驱动器输出元件
页数 文件大小 规格书
18页 512K
描述
OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS

SN54HCT541_07 数据手册

 浏览型号SN54HCT541_07的Datasheet PDF文件第2页浏览型号SN54HCT541_07的Datasheet PDF文件第3页浏览型号SN54HCT541_07的Datasheet PDF文件第4页浏览型号SN54HCT541_07的Datasheet PDF文件第5页浏览型号SN54HCT541_07的Datasheet PDF文件第6页浏览型号SN54HCT541_07的Datasheet PDF文件第7页 
ꢊ ꢅꢆꢋꢌ ꢍꢎꢏ ꢏ ꢐꢑꢀ ꢋꢁꢒ ꢌ ꢓꢁꢐ ꢒ ꢑꢓ ꢔ ꢐꢑ  
SCLS306C − JANUARY 1996 − REVISED AUGUST 2003  
SN54HCT541 . . . J OR W PACKAGE  
SN74HCT541 . . . DB, DW, N, NS, OR PW PACKAGE  
(TOP VIEW)  
D
D
Operating Voltage Range of 4.5 V to 5.5 V  
High-Current 3-State Outputs Interface  
Directly With System Bus or Can Drive Up  
To 15 LSTTL Loads  
OE1  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
V
CC  
OE2  
Y1  
1
2
3
4
5
6
7
8
9
20  
19  
18  
D
D
D
D
D
D
Low Power Consumption, 80-µA Max I  
CC  
Typical t = 12 ns  
pd  
6-mA Output Drive at 5 V  
17 Y2  
16 Y3  
15 Y4  
14 Y5  
13 Y6  
12 Y7  
11 Y8  
Low Input Current of 1 µA Max  
Inputs Are TTL-Voltage Compatible  
Data Flow-Through Pinout (All Inputs on  
Opposite Side From Outputs)  
GND 10  
description/ordering information  
SN54HCT541 . . . FK PACKAGE  
(TOP VIEW)  
These octal buffers and line drivers are designed  
to have the performance of the popular ’HC240  
series devices and to offer a pinout with inputs and  
outputs on opposite sides of the package. This  
arrangement greatly facilitates printed circuit  
board layout.  
3
2
1
20 19  
18  
Y1  
Y2  
Y3  
A3  
A4  
A5  
A6  
A7  
4
5
6
7
8
17  
16  
The 3-state control gate is a 2-input NOR. If either  
output-enable (OE1 or OE2) input is high, all eight  
outputs are in the high-impedance state. The  
’HCT541 devices provide true data at the outputs.  
15 Y4  
14  
Y5  
9 10 11 12 13  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP − N  
Tube of 20  
Tube of 25  
Reel of 2000  
Reel of 2000  
Reel of 2000  
Tube of 70  
Reel of 2000  
Reel of 250  
Tube of 20  
Tube of 85  
Tube of 55  
SN74HCT541N  
SN74HCT541N  
SN74HCT541DW  
SN74HCT541DWR  
SN74HCT541NSR  
SN74HCT541DBR  
SN74HCT541PW  
SN74HCT541PWR  
SN74HCT541PWT  
SNJ54HCT541J  
SOIC − DW  
HCT541  
SOP − NS  
HCT541  
HT541  
−40°C to 85°C  
SSOP − DB  
TSSOP − PW  
HT541  
CDIP − J  
CFP − W  
LCCC − FK  
SNJ54HCT541J  
SNJ54HCT541W  
SNJ54HCT541W  
SNJ54HCT541FK  
−55°C to 125°C  
SNJ54HCT541FK  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
ꢊ ꢚ ꢥ ꢝ ꢜꢨ ꢣꢢ ꢠꢡ ꢢꢜ ꢞꢥ ꢧꢙ ꢟꢚ ꢠ ꢠꢜ ꢯꢓ ꢌꢗ ꢘꢑ ꢏ ꢗꢖꢰꢂ ꢖꢂꢈ ꢟꢧꢧ ꢥꢟ ꢝ ꢟ ꢞꢤ ꢠꢤꢝ ꢡ ꢟ ꢝ ꢤ ꢠꢤ ꢡꢠꢤ ꢨ  
ꢠ ꢤ ꢡ ꢠꢙ ꢚꢮ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢩ  
ꢣ ꢚꢧ ꢤꢡꢡ ꢜ ꢠꢪꢤ ꢝ ꢬꢙ ꢡꢤ ꢚ ꢜꢠꢤ ꢨꢩ ꢊ ꢚ ꢟꢧ ꢧ ꢜ ꢠꢪꢤ ꢝ ꢥꢝ ꢜ ꢨꢣꢢ ꢠꢡ ꢈ ꢥꢝ ꢜ ꢨꢣꢢ ꢠꢙꢜ ꢚ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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