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SN54HCT574_03

更新时间： 2024-10-31 05:05:03
品牌 Logo 应用领域
德州仪器 - TI 触发器输出元件
页数 文件大小 规格书
16页 439K
描述
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

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SN54HCT574_03 数据手册

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SCLS177E − MARCH 1984 − REVISED AUGUST 2003  
SN54HCT574 . . . J OR W PACKAGE  
SN74HCT574 . . . DB, DW, N, NS, OR PW PACKAGE  
(TOP VIEW)  
D
D
Operating Voltage Range of 4.5 V to 5.5 V  
High-Current 3-State Noninverting Outputs  
Drive Bus Lines Directly or Up To 15 LSTTL  
Loads  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
V
CC  
1Q  
2Q  
1
2
3
4
5
6
7
8
9
20  
19  
18  
D
D
D
D
D
D
Low Power Consumption, 80-µA Max I  
CC  
Typical t = 22 ns  
pd  
17 3Q  
16 4Q  
15 5Q  
14 6Q  
13 7Q  
12 8Q  
11 CLK  
6-mA Output Drive at 5 V  
Low Input Current of 1 µA Max  
Inputs Are TTL-Voltage Compatible  
Bus-Structured Pinout  
description/ordering information  
GND 10  
These octal edge-triggered D-type flip-flops  
feature 3-state outputs designed specifically for  
bus driving. The ’HCT574 devices are particularly  
suitable for implementing buffer registers, I/O  
ports, bidirectional bus drivers, and working  
registers.  
SN54HCT574 . . . FK PACKAGE  
(TOP VIEW)  
3
2
1
20 19  
18  
2Q  
3Q  
4Q  
3D  
4D  
5D  
6D  
7D  
4
5
6
7
8
17  
16  
The eight flip-flops enter data on the low-to-high  
transition of the clock (CLK) input.  
15 5Q  
14  
A buffered output-enable (OE) input can be used  
to place the eight outputs in either a normal logic  
state (high or low logic levels) or the  
high-impedance state. In the high-impedance  
state, the outputs neither load nor drive the bus  
lines significantly. The high-impedance state and  
increased drive provide the capability to drive bus  
lines without interface or pullup components.  
6Q  
9 10 11 12 13  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP − N  
Tube of 20  
Tube of 25  
Reel of 2000  
Reel of 2000  
Reel of 2000  
Tube of 70  
Reel of 2000  
Reel of 250  
Tube of 20  
Tube of 85  
Tube of 55  
SN74HCT574N  
SN74HCT574N  
SN74HCT574DW  
SN74HCT574DWR  
SN74HCT574NSR  
SN74HCT574DBR  
SN74HCT574PW  
SN74HCT574PWR  
SN74HCT574PWT  
SNJ54HCT574J  
SOIC − DW  
HCT574  
SOP − NS  
HCT574  
HT574  
−40°C to 85°C  
SSOP − DB  
TSSOP − PW  
HT574  
CDIP − J  
CFP − W  
LCCC − FK  
SNJ54HCT574J  
SNJ54HCT574W  
SNJ54HCT574FK  
SNJ54HCT574W  
SNJ54HCT574FK  
−55°C to 125°C  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
ꢗ ꢁ ꢋꢌꢀꢀ ꢉ ꢆꢄ ꢌꢐꢕ ꢑꢀ ꢌ ꢁ ꢉꢆꢌꢍ ꢘꢙ ꢚꢛ ꢜꢝꢞ ꢟꢠꢡ ꢢꢘ ꢞꢝ ꢢꢘꢣ ꢚꢢꢛ ꢓꢐ ꢉ ꢍ ꢗ ꢅꢆ ꢑꢉ ꢁ  
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ꢦꢣ ꢥ ꢣ ꢠ ꢡ ꢘ ꢡ ꢥ ꢛ ꢩ  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...16

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