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SN54HCT574FK

更新时间： 2024-09-12 23:03:03
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器触发器逻辑集成电路输出元件
页数 文件大小 规格书
6页 118K
描述
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

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SN54HCT574FK 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QLCC包装说明：QCCN, LCC20,.35SQ
针数：20Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01风险等级：5.92
Is Samacsys：N其他特性：BROADSIDE VERSION OF 374
系列：HCTJESD-30 代码：S-CQCC-N20
长度：8.89 mm负载电容（CL）：150 pF
逻辑集成电路类型：BUS DRIVER最大频率@ Nom-Sup：20000000 Hz
最大I（ol）：0.006 A位数：8
功能数量：1端口数量：2
端子数量：20最高工作温度：125 °C
最低工作温度：-55 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：QCCN封装等效代码：LCC20,.35SQ
封装形状：SQUARE封装形式：CHIP CARRIER
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
传播延迟（tpd）：80 ns认证状态：Not Qualified
座面最大高度：2.03 mm子类别：FF/Latches
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子形式：NO LEAD端子节距：1.27 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
触发器类型：POSITIVE EDGE宽度：8.89 mm
Base Number Matches：1

SN54HCT574FK 数据手册

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SN54HCT574, SN74HCT574  
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS  
WITH 3-STATE OUTPUTS  
SCLS177C – MARCH 1984 – REVISED MAY 1997  
SN54HCT574 . . . J OR W PACKAGE  
SN74HCT574 . . . DW, N, OR PW PACKAGE  
(TOP VIEW)  
Inputs Are TTL-Voltage Compatible  
High-Current 3-State Noninverting Outputs  
Drive Bus Lines Directly or up to 15 LSTTL  
Loads  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
V
CC  
1Q  
2Q  
1
2
3
4
5
6
7
8
9
20  
19  
18  
Bus-Structured Pinout  
Package Options Include Plastic  
Small-Outline (DW), Thin Shrink  
Small-Outline (PW), and Ceramic Flat (W)  
Packages, Ceramic Chip Carriers (FK), and  
Standard Plastic (N) and Ceramic (J)  
300-mil DIPs  
17 3Q  
16 4Q  
15 5Q  
14 6Q  
13  
7Q  
12 8Q  
description  
GND 10  
11 CLK  
These octal edge-triggered D-type flip-flops  
feature 3-state outputs designed specifically for  
bus driving. They are particularly suitable for  
implementing buffer registers, I/O ports,  
bidirectional bus drivers, and working registers.  
SN54HCT574 . . . FK PACKAGE  
(TOP VIEW)  
3
2
1
20 19  
18  
The eight flip-flops enter data on the low-to-high  
transition of the clock (CLK) input.  
2Q  
3Q  
4Q  
3D  
4D  
5D  
6D  
7D  
4
5
6
7
8
17  
16  
A buffered output-enable (OE) input can be used  
to place the eight outputs in either a normal logic  
state (high or low logic levels) or the  
high-impedance state. In the high-impedance  
state, the outputs neither load nor drive the bus  
lines significantly. The high-impedance state and  
increased drive provide the capability to drive bus  
lines without interface or pullup components.  
15 5Q  
14  
9 10 11 12 13  
6Q  
OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
The SN54HCT574 is characterized for operation over the full military temperature range of –55°C to 125°C. The  
SN74HCT574 is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
(each flip-flop)  
INPUTS  
OUTPUT  
Q
OE  
L
CLK  
D
H
L
↑
↑
H
L
L
L
H or L  
X
X
X
Q
0
H
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1997, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
123456

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