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SN54HCT573W PDF预览

SN54HCT573W

更新时间： 2024-11-24 13:13:43
品牌 Logo 应用领域
德州仪器 - TI 锁存器输出元件
页数 文件大小 规格书
11页 368K
描述
HCT SERIES, 8-BIT DRIVER, TRUE OUTPUT, CDFP20, CERAMIC, DFP-20

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SN54HCT573W 技术参数

生命周期：Obsolete零件包装代码：DFP
包装说明：DFP,针数：20
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.84系列：HCT
JESD-30 代码：R-GDFP-F20长度：13.09 mm
逻辑集成电路类型：BUS DRIVER位数：8
功能数量：1端口数量：2
端子数量：20最高工作温度：125 °C
最低工作温度：-55 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DFP封装形状：RECTANGULAR
封装形式：FLATPACK传播延迟（tpd）：79 ns
认证状态：Not Qualified座面最大高度：2.54 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子形式：FLAT端子节距：1.27 mm
端子位置：DUAL宽度：6.92 mm
Base Number Matches：1

SN54HCT573W 数据手册

 浏览型号SN54HCT573W的Datasheet PDF文件第2页浏览型号SN54HCT573W的Datasheet PDF文件第3页浏览型号SN54HCT573W的Datasheet PDF文件第4页浏览型号SN54HCT573W的Datasheet PDF文件第5页浏览型号SN54HCT573W的Datasheet PDF文件第6页浏览型号SN54HCT573W的Datasheet PDF文件第7页 
SN54HCT573, SN74HCT573  
OCTAL TRANSPARENT D-TYPE LATCHES  
WITH 3-STATE OUTPUTS  
SCLS176E – MARCH 1984 – REVISED JULY 2003  
SN54HCT573 . . . J OR W PACKAGE  
SN74HCT573 . . . DB, DW, N, NS, OR PW PACKAGE  
(TOP VIEW)  
Operating Voltage Range of 4.5 V to 5.5 V  
High-Current 3-State Outputs Drive Bus  
Lines Directly or Up To 15 LSTTL Loads  
Low Power Consumption, 80-µA Max I  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
V
CC  
1Q  
2Q  
1
2
3
4
5
6
7
8
9
20  
19  
18  
CC  
Typical t = 21 ns  
pd  
±6-mA Output Drive at 5 V  
Low Input Current of 1 µA Max  
Inputs Are TTL-Voltage Compatible  
Bus-Structured Pinout  
17 3Q  
16 4Q  
15 5Q  
14  
6Q  
13 7Q  
12 8Q  
11 LE  
description/ordering information  
GND 10  
These octal transparent D-type latches feature  
3-state outputs designed specifically for driving  
highly capacitive or relatively low-impedance  
loads. The ’HCT573 devices are particularly  
suitable for implementing buffer registers, I/O  
ports, bidirectional bus drivers, and working  
registers.  
SN54HCT573 . . . FK PACKAGE  
(TOP VIEW)  
3
2
1
20 19  
18  
2Q  
3Q  
4Q  
3D  
4D  
5D  
6D  
7D  
4
5
6
7
8
While the latch-enable (LE) input is high, the  
Q outputs respond to the data (D) inputs. When  
LE is low, the outputs are latched to retain the data  
that was set up at the D inputs.  
17  
16  
15 5Q  
14  
9 10 11 12 13  
6Q  
A buffered output-enable (OE) input can be used  
to place the eight outputs in either a normal logic  
state (high or low logic levels) or the  
high-impedance state. In the high-impedance  
state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased  
drive provide the capability to drive bus lines without interface or pullup components.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP – N  
Tube  
SN74HCT573N  
SN74HCT573N  
Tube  
SN74HCT573DW  
SN74HCT573DWR  
SN74HCT573NSR  
SN74HCT573DBR  
SN74HCT573PW  
SN74HCT573PWR  
SNJ54HCT573J  
SNJ54HCT573W  
SNJ54HCT573FK  
SOIC – DW  
HCT573  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
–40°C to 85°C  
SOP – NS  
HCT573  
HT573  
SSOP – DB  
TSSOP – PW  
HT573  
Tape and reel  
Tube  
CDIP – J  
CFP – W  
LCCC – FK  
SNJ54HCT573J  
SNJ54HCT573W  
SNJ54HCT573FK  
–55°C to 125°C  
Tube  
Tube  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...11

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SN54HCT574W TI

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