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SN54HCT377FKR PDF预览

SN54HCT377FKR

更新时间： 2024-11-24 19:42:11
品牌 Logo 应用领域
德州仪器 - TI 输出元件逻辑集成电路触发器
页数 文件大小 规格书
7页 120K
描述
HCT SERIES, OCTAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CQCC20, CERAMIC, LCC-20

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SN54HCT377FKR 技术参数

生命周期：Obsolete零件包装代码：QLCC
包装说明：QCCN,针数：20
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.84其他特性：WITH HOLD MODE
系列：HCTJESD-30 代码：S-CQCC-N20
长度：8.89 mm负载电容（CL）：50 pF
逻辑集成电路类型：D FLIP-FLOP位数：1
功能数量：8端子数量：20
最高工作温度：125 °C最低工作温度：-55 °C
输出极性：TRUE封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：QCCN封装形状：SQUARE
封装形式：CHIP CARRIER传播延迟（tpd）：45 ns
认证状态：Not Qualified座面最大高度：2.03 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子形式：NO LEAD端子节距：1.27 mm
端子位置：QUAD触发器类型：POSITIVE EDGE
宽度：8.89 mm最小 fmax：19 MHz
Base Number Matches：1

SN54HCT377FKR 数据手册

 浏览型号SN54HCT377FKR的Datasheet PDF文件第2页浏览型号SN54HCT377FKR的Datasheet PDF文件第3页浏览型号SN54HCT377FKR的Datasheet PDF文件第4页浏览型号SN54HCT377FKR的Datasheet PDF文件第5页浏览型号SN54HCT377FKR的Datasheet PDF文件第6页浏览型号SN54HCT377FKR的Datasheet PDF文件第7页 
SN54HCT377, SN74HCT377  
OCTAL D-TYPE FLIP-FLOPS  
WITH CLOCK ENABLE  
SCLS067C – NOVEMBER 1988 – REVISED MAY 1997  
SN54HCT377 . . . J OR W PACKAGE  
SN74HCT377 . . . DW OR N PACKAGE  
(TOP VIEW)  
Inputs Are TTL-Voltage Compatible  
Contain Eight Flip-Flops With Single-Rail  
Outputs  
Clock Enable Latched to Avoid False  
Clocking  
CLKEN  
1Q  
V
CC  
8Q  
8D  
1
2
3
4
5
6
7
8
9
20  
19  
18  
1D  
Applications Include:  
– Buffer/Storage Registers  
– Shift Registers  
2D  
17 7D  
16 7Q  
15 6Q  
14 6D  
13 5D  
12 5Q  
11 CLK  
2Q  
3Q  
– Pattern Generators  
3D  
Package Options Include Plastic  
Small-Outline (DW), and Ceramic Flat (W)  
Packages, Ceramic Chip Carriers (FK), and  
Standard Plastic (N) and Ceramic (J)  
300-mil DIPs  
4D  
4Q  
GND 10  
SN54HCT377 . . . FK PACKAGE  
(TOP VIEW)  
description  
Thesedevicesarepositive-edge-triggeredD-type  
flip-flops. The ’HCT377 are similar to the ’HCT273  
but feature a latched clock-enable (CLKEN) input  
instead of a common clear.  
3
2
1
20 19  
18  
8D  
7D  
7Q  
2D  
2Q  
3Q  
3D  
4D  
4
5
6
7
8
Information at the data (D) inputs meeting the  
setup time requirements is transferred to the  
Q outputs on the positive-going edge of the clock  
(CLK) pulse if CLKEN is low. Clock triggering  
occurs at a particular voltage level and is not  
directly related to the transition time of the  
positive-going pulse. When CLK is at either the  
high or low level, the D input has no effect at the  
output. These devices are designed to prevent  
false clocking by transitions at CLKEN.  
17  
16  
15 6Q  
14  
9 10 11 12 13  
6D  
The SN54HCT377 is characterized for operation over the full military temperature range of –55°C to 125°C. The  
SN74HCT377 is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
(each flip-flop)  
INPUTS  
OUTPUT  
Q
CLKEN CLK  
D
X
H
L
H
L
X
↑
Q
0
H
L
↑
L
X
L
X
Q
0
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1997, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567

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