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SN54HCT377J PDF预览

SN54HCT377J

更新时间： 2024-11-04 23:03:03
品牌 Logo 应用领域
德州仪器 - TI 触发器锁存器逻辑集成电路时钟
页数 文件大小 规格书
9页 273K
描述
OCTAL D-TYPE FLIP-FLOPS WITH CLOCK ENABLE

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中文翻译

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SN54HCT377J 技术参数

生命周期：Obsolete零件包装代码：DIP
包装说明：DIP,针数：20
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.49其他特性：WITH HOLD MODE
系列：HCTJESD-30 代码：R-GDIP-T20
长度：24.195 mm负载电容（CL）：50 pF
逻辑集成电路类型：D FLIP-FLOP位数：1
功能数量：8端子数量：20
最高工作温度：125 °C最低工作温度：-55 °C
输出极性：TRUE封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DIP封装形状：RECTANGULAR
封装形式：IN-LINE传播延迟（tpd）：45 ns
认证状态：Not Qualified座面最大高度：5.08 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：CMOS温度等级：MILITARY
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL触发器类型：POSITIVE EDGE
宽度：7.62 mm最小 fmax：19 MHz
Base Number Matches：1

SN54HCT377J 数据手册

 浏览型号SN54HCT377J的Datasheet PDF文件第2页浏览型号SN54HCT377J的Datasheet PDF文件第3页浏览型号SN54HCT377J的Datasheet PDF文件第4页浏览型号SN54HCT377J的Datasheet PDF文件第5页浏览型号SN54HCT377J的Datasheet PDF文件第6页浏览型号SN54HCT377J的Datasheet PDF文件第7页 
SN54HCT377, SN74HCT377  
OCTAL D-TYPE FLIP-FLOPS  
WITH CLOCK ENABLE  
SCLS067D – NOVEMBER 1988 – REVISED MARCH 2003  
Operating Voltage Range of 4.5 V to 5.5 V  
Outputs Can Drive Up To 10 LSTTL Loads  
Contain Eight Flip-Flops With Single-Rail  
Outputs  
Clock Enable Latched to Avoid False  
Clocking  
Low Power Consumption, 80-µA Max I  
CC  
Typical t = 12 ns  
pd  
±4-mA Output Drive at 5 V  
Applications Include:  
– Buffer/Storage Registers  
– Shift Registers  
Low Input Current of 1 µA Max  
Inputs Are TTL-Voltage Compatible  
– Pattern Generators  
SN54HCT377 . . . FK PACKAGE  
(TOP VIEW)  
SN54HCT377 . . . J OR W PACKAGE  
SN74HCT377 . . . DW OR N PACKAGE  
(TOP VIEW)  
CLKEN  
1Q  
V
CC  
1
2
3
4
5
6
7
8
9
20  
19 8Q  
18 8D  
17 7D  
16 7Q  
15 6Q  
14 6D  
13 5D  
12 5Q  
11 CLK  
3
2
1
20 19  
18  
1D  
8D  
7D  
7Q  
2D  
2Q  
3Q  
3D  
4D  
4
5
6
7
8
2D  
17  
16  
2Q  
3Q  
15 6Q  
14  
9 10 11 12 13  
3D  
6D  
4D  
4Q  
GND 10  
description/ordering information  
These devices are positive-edge-triggered D-type flip-flops. The ’HCT377 devices are similar to the ’HCT273  
devices, but feature a latched clock-enable (CLKEN) input instead of a common clear.  
Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the  
positive-going edge of the clock (CLK) pulse if CLKEN is low. Clock triggering occurs at a particular voltage level  
and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or  
low level, the D input has no effect at the output. These devices are designed to prevent false clocking by  
transitions at CLKEN.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP – N  
Tube  
SN74HCT377N  
SN74HCT377N  
–40°C to 85°C  
–55°C to 125°C  
Tube  
SN74HCT377DW  
SN74HCT377DWR  
SNJ54HCT377J  
SNJ54HCT377W  
SNJ54HCT377FK  
SOIC – DW  
HCT377  
Tape and reel  
Tube  
CDIP – J  
CFP – W  
LCCC – FK  
SNJ54HCT377J  
SNJ54HCT377W  
SNJ54HCT377FK  
Tube  
Tube  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

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