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SN54HCT00J PDF预览

SN54HCT00J

更新时间: 2024-11-03 23:03:03
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德州仪器 - TI 输入元件
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4页 80K
描述
QUADRUPLE 2-INPUT POSITIVE-NAND GATES

SN54HCT00J 技术参数

生命周期:Obsolete零件包装代码:DIP
包装说明:DIP, DIP14,.3针数:14
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.57系列:HCT
JESD-30 代码:R-GDIP-T14长度:19.56 mm
负载电容(CL):50 pF逻辑集成电路类型:NAND GATE
最大I(ol):0.004 A功能数量:4
输入次数:2端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装等效代码:DIP14,.3封装形状:RECTANGULAR
封装形式:IN-LINE电源:5 V
Prop。Delay @ Nom-Sup:30 ns传播延迟(tpd):30 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:5.08 mm子类别:Gates
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL宽度:7.62 mm
Base Number Matches:1

SN54HCT00J 数据手册

 浏览型号SN54HCT00J的Datasheet PDF文件第2页浏览型号SN54HCT00J的Datasheet PDF文件第3页浏览型号SN54HCT00J的Datasheet PDF文件第4页 
SN54HCT00, SN74HCT00  
QUADRUPLE 2-INPUT POSITIVE-NAND GATES  
SCLS062B – NOVEMBER 1988 – REVISED MAY 1997  
SN54HCT00 . . . J OR W PACKAGE  
SN74HCT00 . . . D, N, OR PW PACKAGE  
(TOP VIEW)  
Inputs Are TTL-Voltage Compatible  
Package Options Include Plastic  
Small-Outline (D), Thin Shrink  
Small-Outline (PW), and Ceramic Flat (W)  
Packages, Ceramic Chip Carriers (FK), and  
Standard Plastic (N) and Ceramic (J)  
300-mil DIPs  
1A  
1B  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
4B  
4A  
4Y  
1Y  
2A  
2B  
10 3B  
description  
9
8
2Y  
3A  
3Y  
These devices contain four independent 2-input  
NAND gates. They perform the Boolean function  
Y = A B or Y = A + B in positive logic.  
GND  
SN54HCT00 . . . FK PACKAGE  
(TOP VIEW)  
The SN54HCT00 is characterized for operation  
over the full military temperature range of –55°C  
to 125°C. The SN74HCT00 is characterized for  
operation from –40°C to 85°C.  
3
2
1
20 19  
18  
4A  
NC  
4Y  
1Y  
NC  
2A  
4
5
6
7
8
17  
16  
FUNCTION TABLE  
(each gate)  
INPUTS  
15 NC  
14  
9 10 11 12 13  
NC  
2B  
OUTPUT  
Y
3B  
A
H
L
B
H
X
L
L
H
H
X
NC – No internal connection  
logic symbol  
1
1A  
&
3
2
1Y  
1B  
2A  
2B  
3A  
3B  
4A  
4B  
4
6
5
2Y  
9
8
10  
12  
13  
3Y  
11  
4Y  
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.  
Pin numbers shown are for the D, J, N, PW, and W packages.  
logic diagram (positive logic)  
A
B
Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1997, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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