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SN54HCT08W PDF预览

SN54HCT08W

更新时间: 2024-11-25 23:03:03
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德州仪器 - TI 输入元件
页数 文件大小 规格书
4页 80K
描述
QUADRUPLE 2-INPUT POSITIVE-AND GATES

SN54HCT08W 技术参数

生命周期:Obsolete零件包装代码:DFP
包装说明:DFP,针数:14
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.83系列:HCT
JESD-30 代码:R-GDFP-F14长度:9.21 mm
负载电容(CL):50 pF逻辑集成电路类型:AND GATE
功能数量:4输入次数:2
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DFP封装形状:RECTANGULAR
封装形式:FLATPACK传播延迟(tpd):35 ns
认证状态:Not Qualified座面最大高度:2.03 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:FLAT端子节距:1.27 mm
端子位置:DUAL宽度:6.29 mm

SN54HCT08W 数据手册

 浏览型号SN54HCT08W的Datasheet PDF文件第2页浏览型号SN54HCT08W的Datasheet PDF文件第3页浏览型号SN54HCT08W的Datasheet PDF文件第4页 
SN54HCT08, SN74HCT08  
QUADRUPLE 2-INPUT POSITIVE-AND GATES  
SCLS063B – NOVEMBER 1988 – REVISED MAY 1997  
SN54HCT08 . . . J OR W PACKAGE  
SN74HCT08 . . . D, DB, N, OR PW PACKAGE  
(TOP VIEW)  
Inputs Are TTL-Voltage Compatible  
Package Options Include Plastic  
Small-Outline (D), Shrink Small-Outline  
(DB), Thin Shrink Small-Outline (PW), and  
Ceramic Flat (W) Packages, Ceramic Chip  
Carriers (FK), and Standard Plastic (N) and  
Ceramic (J) 300-mil DIPs  
1A  
1B  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
4B  
4A  
4Y  
1Y  
2A  
2B  
10 3B  
description  
9
8
2Y  
3A  
3Y  
GND  
These devices contain four independent 2-input  
AND gates. They perform the Boolean function  
Y
A B or Y  
A
B
in positive logic.  
SN54HCT08 . . . FK PACKAGE  
(TOP VIEW)  
The SN54HCT08 is characterized for operation  
over the full military temperature range of –55°C  
to 125°C. The SN74HCT08 is characterized for  
operation from –40°C to 85°C.  
3
2
1
20 19  
18  
4A  
NC  
4Y  
1Y  
NC  
2A  
4
5
6
7
8
17  
16  
FUNCTION TABLE  
(each gate)  
15 NC  
14  
9 10 11 12 13  
NC  
2B  
INPUTS  
OUTPUT  
Y
3B  
A
B
H
X
L
H
L
H
L
L
X
NC – No internal connection  
logic symbol  
1
1A  
2
&
3
1Y  
1B  
4
2A  
5
6
2Y  
2B  
9
3A  
8
10  
3Y  
3B  
4A  
4B  
12  
13  
11  
4Y  
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.  
Pin numbers shown are for the D, DB, J, N, PW, and W packages.  
logic diagram (positive logic)  
A
B
Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1997, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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