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SN54HCT125WR PDF预览

SN54HCT125WR

更新时间: 2024-11-04 20:42:03
品牌 Logo 应用领域
德州仪器 - TI 驱动输出元件逻辑集成电路
页数 文件大小 规格书
5页 95K
描述
HCT SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, CDFP14, CERAMIC, FP-14

SN54HCT125WR 技术参数

生命周期:Obsolete零件包装代码:DFP
包装说明:DFP,针数:14
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.82系列:HCT
JESD-30 代码:R-GDFP-F14长度:9.21 mm
负载电容(CL):150 pF逻辑集成电路类型:BUS DRIVER
位数:1功能数量:4
端口数量:2端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DFP
封装形状:RECTANGULAR封装形式:FLATPACK
传播延迟(tpd):58 ns认证状态:Not Qualified
座面最大高度:2.03 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子形式:FLAT
端子节距:1.27 mm端子位置:DUAL
宽度:6.29 mmBase Number Matches:1

SN54HCT125WR 数据手册

 浏览型号SN54HCT125WR的Datasheet PDF文件第2页浏览型号SN54HCT125WR的Datasheet PDF文件第3页浏览型号SN54HCT125WR的Datasheet PDF文件第4页浏览型号SN54HCT125WR的Datasheet PDF文件第5页 
SN54HCT125, SN74HCT125  
QUADRUPLE BUS BUFFER GATES  
WITH 3-STATE OUTPUTS  
SCLS069C – NOVEMBER 1988 – REVISED MAY 1997  
SN54HCT125 . . . J OR W PACKAGE  
SN74HCT125 . . . D OR N PACKAGE  
(TOP VIEW)  
Inputs Are TTL-Voltage Compatible  
High-Current 3-State Outputs Drive Bus  
Lines or Buffer Memory Address Registers  
Package Options Include Plastic  
Small-Outline (D) and Ceramic Flat (W)  
Packages, Ceramic Chip Carriers (FK), and  
Standard Plastic (N) and Ceramic (J)  
300-mil DIPs  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
1OE  
1A  
1Y  
2OE  
2A  
2Y  
V
CC  
4OE  
4A  
4Y  
3OE  
3A  
description  
8
GND  
3Y  
These bus buffer gates feature independent line  
drivers with 3-state outputs. Each output is  
disasbled when the associated output-enable  
(OE) input is high.  
SN54HCT125 . . . FK PACKAGE  
(TOP VIEW)  
The SN54HCT125 is characterized for operation  
over the full military temperature range of –55°C  
to 125°C. The SN74HCT125 is characterized for  
operation from –40°C to 85°C.  
3
2
1
20 19  
18  
4A  
NC  
4Y  
1Y  
NC  
4
5
6
7
8
17  
16  
2OE  
NC  
15 NC  
14  
9 10 11 12 13  
FUNCTION TABLE  
(each gate)  
3OE  
2A  
INPUTS  
OUTPUT  
Y
OE  
A
H
L
L
L
H
L
NC – No internal connection  
H
X
Z
logic symbol  
1
1OE  
2
EN  
3
1Y  
1B  
4
2OE  
5
6
2Y  
2B  
10  
3OE  
3B  
8
9
3Y  
13  
12  
4OE  
4B  
11  
4Y  
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.  
Pin numbers shown are for the D, J, N, and W packages.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1997, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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