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SN54HCT14J PDF预览

SN54HCT14J

更新时间: 2024-11-03 23:03:03
品牌 Logo 应用领域
德州仪器 - TI 栅极逻辑集成电路
页数 文件大小 规格书
6页 88K
描述
HEX SCHMITT-TRIGGER INVERTERS

SN54HCT14J 技术参数

生命周期:Obsolete零件包装代码:DIP
包装说明:CERAMIC, DIP-14针数:14
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.16Is Samacsys:N
系列:HCTJESD-30 代码:R-GDIP-T14
长度:19.56 mm负载电容(CL):50 pF
逻辑集成电路类型:INVERTER功能数量:6
输入次数:1端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
传播延迟(tpd):48 ns认证状态:Not Qualified
座面最大高度:5.08 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
宽度:7.62 mmBase Number Matches:1

SN54HCT14J 数据手册

 浏览型号SN54HCT14J的Datasheet PDF文件第2页浏览型号SN54HCT14J的Datasheet PDF文件第3页浏览型号SN54HCT14J的Datasheet PDF文件第4页浏览型号SN54HCT14J的Datasheet PDF文件第5页浏览型号SN54HCT14J的Datasheet PDF文件第6页 
SN54HCT14, SN74HCT14  
HEX SCHMITT-TRIGGER INVERTERS  
SCLS225C – JULY 1995 – REVISED FEBRUARY 2000  
SN54HCT14 . . . J OR W PACKAGE  
SN74HCT14 . . . D, DB, DGV, N, OR PW PACKAGE  
(TOP VIEW)  
Inputs Are TTL-Voltage Compatible  
Package Options Include Plastic  
Small-Outline (D), Shrink Small-Outline  
(DB), Thin Very Small-Outline (DGV), Thin  
Shrink Small-Outline (PW), and Ceramic  
Flat (W) Packages, Ceramic Chip Carriers  
(FK), and Standard Plastic (N) and Ceramic  
(J) DIPs  
1A  
1Y  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
6A  
6Y  
5A  
2A  
2Y  
3A  
10 5Y  
9
8
3Y  
4A  
4Y  
description  
GND  
The ’HCT14 devices contain six independent  
inverters. The devices perform the Boolean  
function Y = A in positive logic.  
SN54HCT14 . . . FK PACKAGE  
(TOP VIEW)  
The SN54HCT14 is characterized for operation  
over the full military temperature range of –55°C  
to 125°C. The SN74HCT14 is characterized for  
operation from –40°C to 85°C.  
3
2
1
20 19  
18  
6Y  
NC  
5A  
2A  
NC  
2Y  
4
5
6
7
8
17  
16  
FUNCTION TABLE  
(each inverter)  
15 NC  
14  
9 10 11 12 13  
NC  
3A  
INPUT  
A
OUTPUT  
Y
5Y  
H
L
L
H
NC – No internal connection  
logic symbol  
2
1
1Y  
1A  
2A  
3A  
4A  
5A  
6A  
3
4
2Y  
6
5
3Y  
8
9
4Y  
11  
13  
10  
5Y  
12  
6Y  
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.  
Pin numbers shown are for the D, DB, DGV, J, N, PW, and W packages.  
logic diagram (positive logic)  
A
Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2000, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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