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SN54HCT139J PDF预览

SN54HCT139J

更新时间： 2024-09-27 23:03:03
品牌 Logo 应用领域
德州仪器 - TI 解码器驱动器解复用器逻辑集成电路
页数 文件大小 规格书
5页 96K
描述
DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS

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SN54HCT139J 技术参数

生命周期：Obsolete零件包装代码：DIP
包装说明：0.300 INCH, CERAMIC, DIP-16针数：16
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.38
Is Samacsys：N系列：HCT
JESD-30 代码：R-GDIP-T16长度：19.56 mm
负载电容（CL）：50 pF逻辑集成电路类型：OTHER DECODER/DRIVER
最大I（ol）：0.004 A功能数量：2
端子数量：16最高工作温度：125 °C
最低工作温度：-55 °C输出极性：INVERTED
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DIP
封装等效代码：DIP16,.3封装形状：RECTANGULAR
封装形式：IN-LINE电源：5 V
Prop。Delay @ Nom-Sup：51 ns传播延迟（tpd）：51 ns
认证状态：Not Qualified座面最大高度：5.08 mm
子类别：Decoder/Drivers最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：NO技术：CMOS
温度等级：MILITARY端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
宽度：7.62 mmBase Number Matches：1

SN54HCT139J 数据手册

 浏览型号SN54HCT139J的Datasheet PDF文件第2页浏览型号SN54HCT139J的Datasheet PDF文件第3页浏览型号SN54HCT139J的Datasheet PDF文件第4页浏览型号SN54HCT139J的Datasheet PDF文件第5页 
SN54HCT139, SN74HCT139  
DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS  
SCLS066B – MARCH 1982 – REVISED MAY 1997  
SN54HCT139 . . . J OR W PACKAGE  
SN74HCT139 . . . D, DB, N, OR PW PACKAGE  
(TOP VIEW)  
Inputs Are TTL-Voltage Compatible  
Designed Specifically for High-Speed  
Memory Decoders and Data Transmission  
Systems  
1G  
1A  
V
CC  
2G  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
Incorporate Two Enable Inputs to Simplify  
Cascading and/or Data Reception  
1B  
2A  
1Y0  
1Y1  
1Y2  
1Y3  
GND  
2B  
Package Options Include Plastic  
Small-Outline (D), Shrink Small-Outline  
(DB), Thin Shrink Small-Outline (PW), and  
Ceramic Flat (W) Packages, Ceramic Chip  
Carriers (FK), and Standard Plastic (N) and  
Ceramic (J) 300-mil DIPs  
2Y0  
2Y1  
2Y2  
2Y3  
SN54HCT139 . . . FK PACKAGE  
(TOP VIEW)  
description  
The ’HCT139 are designed for high-performance  
memory-decoding or data-routing applications  
requiring very short propagation delay times. In  
high-performance memory systems, these  
decoders can minimize the effects of system  
decoding. When employed with high-speed  
memories utilizing a fast enable circuit, the delay  
time of these decoders and the enable time of the  
memory are usually less than the typical access  
time of the memory. This means that the effective  
system delay introduced by the decoders is  
negligible.  
3
2
1
20 19  
18  
2A  
2B  
NC  
1B  
1Y0  
NC  
4
5
6
7
8
17  
16  
15 2Y0  
14  
9 10 11 12 13  
1Y1  
1Y2  
2Y1  
NC – No internal connection  
The ’HCT139 comprise two individual 2-line to  
4-line decoders in a single package. The  
active-low enable (G) input can be used as a data  
line in demultiplexing applications. These  
decoders/demultiplexers feature fully buffered  
inputs, each of which represents only one  
normalized load to its driving circuit.  
The SN54HCT139 is characterized for operation over the full military temperature range of –55°C to 125°C. The  
SN74HCT139 is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
INPUTS  
OUTPUTS  
SELECT  
G
B
X
L
A
X
L
Y0  
H
L
Y1  
H
H
L
Y2  
H
H
H
L
Y3  
H
H
H
H
L
H
L
L
L
L
L
H
L
H
H
H
H
H
H
H
H
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1997, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
12345

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