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SN54HCT138W PDF预览

SN54HCT138W

更新时间： 2024-11-03 23:03:03
品牌 Logo 应用领域
德州仪器 - TI 解码器驱动器解复用器逻辑集成电路输入元件
页数 文件大小 规格书
6页 97K
描述
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

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中文翻译

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SN54HCT138W 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：DFP包装说明：DFP, FL16,.3
针数：16Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.43其他特性：3 ENABLE INPUTS
系列：HCT输入调节：STANDARD
JESD-30 代码：R-GDFP-F16长度：10.2 mm
负载电容（CL）：50 pF逻辑集成电路类型：OTHER DECODER/DRIVER
最大I（ol）：0.004 A功能数量：1
端子数量：16最高工作温度：125 °C
最低工作温度：-55 °C输出极性：INVERTED
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DFP
封装等效代码：FL16,.3封装形状：RECTANGULAR
封装形式：FLATPACK峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5 VProp。Delay @ Nom-Sup：54 ns
传播延迟（tpd）：54 ns认证状态：Not Qualified
座面最大高度：2.03 mm子类别：Decoder/Drivers
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子形式：FLAT端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：6.73 mmBase Number Matches：1

SN54HCT138W 数据手册

 浏览型号SN54HCT138W的Datasheet PDF文件第2页浏览型号SN54HCT138W的Datasheet PDF文件第3页浏览型号SN54HCT138W的Datasheet PDF文件第4页浏览型号SN54HCT138W的Datasheet PDF文件第5页浏览型号SN54HCT138W的Datasheet PDF文件第6页 
SN54HCT138, SN74HCT138  
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS  
SCLS171C – MARCH 1984 – REVISED MAY 1997  
SN54HCT138 . . . J OR W PACKAGE  
SN74HCT138 . . . D, N, OR PW PACKAGE  
(TOP VIEW)  
Inputs Are TTL-Voltage Compatible  
Designed Specifically for High-Speed  
Memory Decoders and Data Transmission  
Systems  
A
B
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
Y0  
Y1  
Y2  
Incorporate Three Enable Inputs to Simplify  
Cascading and/or Data Reception  
C
G2A  
G2B  
G1  
Package Options Include Plastic  
Small-Outline (D), Thin Shrink  
Small-Outline (PW), and Ceramic Flat (W)  
Packages, Ceramic Chip Carriers (FK), and  
Standard Plastic (N) and Ceramic (J)  
300-mil DIPs  
12 Y3  
11  
10  
9
Y4  
Y5  
Y6  
Y7  
GND  
SN54HCT138 . . . FK PACKAGE  
(TOP VIEW)  
description  
The ’HCT138 are designed for high-performance  
memory-decoding or data-routing applications  
requiring very short propagation delay times. In  
high-performance memory systems, these  
decoders can minimize the effects of system  
decoding. When employed with high-speed  
memories utilizing a fast enable circuit, the delay  
timesofthesedecodersandtheenabletimeofthe  
memory are usually less than the typical access  
time of the memory. This means that the effective  
system delay introduced by the decoders is  
negligible.  
3
2
1
20 19  
18  
Y1  
Y2  
NC  
C
G2A  
NC  
4
5
6
7
8
17  
16  
15 Y3  
14  
9 10 11 12 13  
G2B  
G1  
Y4  
NC – No internal connection  
The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two  
active-low (G) and one active-high (G) enable inputs reduce the need for external gates or inverters when  
expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires  
only one inverter. An enable input can be used as a data input for demultiplexing applications.  
The SN54HCT138 is characterized for operation over the full military temperature range of –55°C to 125°C. The  
SN74HCT138 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1997, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
123456

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