SN54F175, SN74F175
QUADRUPLE D-TYPE FLIP-FLOPS
WITH CLEAR
SDFS058A – D2932, MARCH 1987 – REVISED OCTOBER 1993
SN54F175 . . . J PACKAGE
SN74F175 . . . D OR N PACKAGE
(TOP VIEW)
• Contain Four Flip-Flops With Double-Rail
Outputs
• Buffered Clock and Direct Clear Inputs
• Applications Include:
Buffer/Storage Registers
Shift Registers
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CLR
1Q
1Q
1D
2D
2Q
2Q
GND
CC
4Q
4Q
4D
3D
3Q
3Q
CLK
Pattern Generators
• Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Plastic and Ceramic
300-mil DIPs
description
SN54F175 . . . FK PACKAGE
(TOP VIEW)
These monolithic, positive-edge-triggered flip-
flops utilize TTL circuitry to implement D-type
flip-flop logic with a direct clear (CLR) input.
Information at the data (D) inputs meeting setup
time requirements is transferred to outputs on the
positive-going edge of the clock pulse. Clock
triggering occurs at a particular voltage level and
is not directly related to the transition time of the
positive-going pulse. When the clock (CLK) input
is at either the high or low level, the D-input signal
has no effect at the output.
3
2
1
20 19
18
4Q
4D
NC
3D
3Q
1Q
1D
NC
2D
2Q
4
5
6
7
8
17
16
15
14
9 10 11 12 13
The SN54F175 is characterized for operation over
the full military temperature range of –55°C to
125°C. The SN74F175 is characterized for
operation from 0°C to 70°C.
NC – No internal connection
FUNCTION TABLE
INPUTS
OUTPUTS
CLR
L
CLK
D
X
H
L
Q
L
Q
H
L
X
↑
H
H
L
H
↑
H
H
L
X
Q
Q
0
0
Copyright 1993, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
2–1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265