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SN54F175FK PDF预览

SN54F175FK

更新时间: 2024-10-30 22:40:51
品牌 Logo 应用领域
德州仪器 - TI 触发器逻辑集成电路
页数 文件大小 规格书
5页 75K
描述
QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

SN54F175FK 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QLCC包装说明:QCCN, LCC20,.35SQ
针数:20Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.47
系列:F/FASTJESD-30 代码:S-CQCC-N20
长度:8.89 mm负载电容(CL):50 pF
逻辑集成电路类型:D FLIP-FLOP最大频率@ Nom-Sup:100000000 Hz
最大I(ol):0.02 A位数:4
功能数量:1端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:COMPLEMENTARY封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:QCCN封装等效代码:LCC20,.35SQ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
最大电源电流(ICC):34 mA传播延迟(tpd):10.5 ns
认证状态:Not Qualified座面最大高度:2.03 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:MILITARY端子形式:NO LEAD
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:8.89 mm最小 fmax:100 MHz
Base Number Matches:1

SN54F175FK 数据手册

 浏览型号SN54F175FK的Datasheet PDF文件第2页浏览型号SN54F175FK的Datasheet PDF文件第3页浏览型号SN54F175FK的Datasheet PDF文件第4页浏览型号SN54F175FK的Datasheet PDF文件第5页 
SN54F175, SN74F175  
QUADRUPLE D-TYPE FLIP-FLOPS  
WITH CLEAR  
SDFS058A – D2932, MARCH 1987 – REVISED OCTOBER 1993  
SN54F175 . . . J PACKAGE  
SN74F175 . . . D OR N PACKAGE  
(TOP VIEW)  
Contain Four Flip-Flops With Double-Rail  
Outputs  
Buffered Clock and Direct Clear Inputs  
Applications Include:  
Buffer/Storage Registers  
Shift Registers  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
V
CLR  
1Q  
1Q  
1D  
2D  
2Q  
2Q  
GND  
CC  
4Q  
4Q  
4D  
3D  
3Q  
3Q  
CLK  
Pattern Generators  
Package Options Include Plastic  
Small-Outline Packages, Ceramic Chip  
Carriers, and Standard Plastic and Ceramic  
300-mil DIPs  
description  
SN54F175 . . . FK PACKAGE  
(TOP VIEW)  
These monolithic, positive-edge-triggered flip-  
flops utilize TTL circuitry to implement D-type  
flip-flop logic with a direct clear (CLR) input.  
Information at the data (D) inputs meeting setup  
time requirements is transferred to outputs on the  
positive-going edge of the clock pulse. Clock  
triggering occurs at a particular voltage level and  
is not directly related to the transition time of the  
positive-going pulse. When the clock (CLK) input  
is at either the high or low level, the D-input signal  
has no effect at the output.  
3
2
1
20 19  
18  
4Q  
4D  
NC  
3D  
3Q  
1Q  
1D  
NC  
2D  
2Q  
4
5
6
7
8
17  
16  
15  
14  
9 10 11 12 13  
The SN54F175 is characterized for operation over  
the full military temperature range of 55°C to  
125°C. The SN74F175 is characterized for  
operation from 0°C to 70°C.  
NC – No internal connection  
FUNCTION TABLE  
INPUTS  
OUTPUTS  
CLR  
L
CLK  
D
X
H
L
Q
L
Q
H
L
X
H
H
L
H
H
H
L
X
Q
Q
0
0
Copyright 1993, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
2–1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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