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SN54F20FK PDF预览

SN54F20FK

更新时间: 2024-10-30 22:53:39
品牌 Logo 应用领域
德州仪器 - TI 输入元件
页数 文件大小 规格书
5页 70K
描述
DUAL 4-INPUT POSITIVE-NAND GATES

SN54F20FK 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QLCC包装说明:QCCN, LCC20,.35SQ
针数:20Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.46
系列:F/FASTJESD-30 代码:S-CQCC-N20
长度:8.89 mm负载电容(CL):50 pF
逻辑集成电路类型:NAND GATE功能数量:2
输入次数:4端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:QCCN
封装等效代码:LCC20,.35SQ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V最大电源电流(ICC):5.1 mA
传播延迟(tpd):6.5 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:2.03 mm
子类别:Gates最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:MILITARY端子形式:NO LEAD
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:8.89 mm

SN54F20FK 数据手册

 浏览型号SN54F20FK的Datasheet PDF文件第2页浏览型号SN54F20FK的Datasheet PDF文件第3页浏览型号SN54F20FK的Datasheet PDF文件第4页浏览型号SN54F20FK的Datasheet PDF文件第5页 
SN54F20, SN74F20  
DUAL 4-INPUT POSITIVE-NAND GATES  
SDFS041A – MARCH 1987 – REVISED OCTOBER 1993  
SN54F20 . . . J PACKAGE  
SN74F20 . . . D OR N PACKAGE  
(TOP VIEW)  
Package Options Include Plastic  
Small-Outline Packages, Ceramic Chip  
Carriers, and Standard Plastic and Ceramic  
300-mil DIPs  
1A  
1B  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
2D  
2C  
NC  
2B  
2A  
2Y  
description  
NC  
1C  
These devices contain two independent 4-input  
NAND gates. They perform the Boolean functions  
Y = A B C D or Y = A + B + C + D in positive  
logic.  
1D  
1Y  
GND  
8
The SN54F20 is characterized for operation over  
the full military temperature range of 55°C to  
125°C. The SN74F20 is characterized for  
operation from 0°C to 70°C.  
SN54F20 . . . FK PACKAGE  
(TOP VIEW)  
FUNCTION TABLE  
(each gate)  
3
2
1
20 19  
18  
NC  
NC  
1C  
NC  
1D  
2C  
NC  
NC  
NC  
2B  
4
5
6
7
8
INPUTS  
OUTPUT  
Y
17  
16  
15  
14  
A
H
L
B
C
H
X
X
L
D
H
X
X
X
L
H
X
L
L
H
H
H
H
9 10 11 12 13  
X
X
X
X
X
X
NC – No internal connection  
logic symbol  
1
&
1A  
1B  
1C  
1D  
2
4
5
6
1Y  
9
2A  
2B  
2C  
2D  
10  
12  
13  
8
2Y  
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.  
Pin numbers shown are for the D, J, and N packages.  
logic diagram, each gate (positive logic)  
A
B
C
D
Y
Copyright 1993, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
2–1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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