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SN54F242FKR PDF预览

SN54F242FKR

更新时间： 2024-11-18 20:00:23
品牌 Logo 应用领域
德州仪器 - TI 输出元件逻辑集成电路
页数 文件大小 规格书
5页 75K
描述
F/FAST SERIES, 4-BIT TRANSCEIVER, INVERTED OUTPUT, CQCC20, CERAMIC, LCC-20

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SN54F242FKR 技术参数

生命周期：Obsolete零件包装代码：QLCC
包装说明：QCCN,针数：20
Reach Compliance Code：unknown风险等级：5.76
其他特性：WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION系列：F/FAST
JESD-30 代码：S-CQCC-N20长度：8.89 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS TRANSCEIVER
位数：4功能数量：1
端口数量：2端子数量：20
最高工作温度：125 °C最低工作温度：-55 °C
输出特性：3-STATE输出极性：INVERTED
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：QCCN
封装形状：SQUARE封装形式：CHIP CARRIER
最大电源电流（ICC）：69 mA传播延迟（tpd）：5 ns
认证状态：Not Qualified座面最大高度：2.03 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：TTL温度等级：MILITARY
端子形式：NO LEAD端子节距：1.27 mm
端子位置：QUAD宽度：8.89 mm
Base Number Matches：1

SN54F242FKR 数据手册

 浏览型号SN54F242FKR的Datasheet PDF文件第2页浏览型号SN54F242FKR的Datasheet PDF文件第3页浏览型号SN54F242FKR的Datasheet PDF文件第4页浏览型号SN54F242FKR的Datasheet PDF文件第5页 
SN54F242, SN74F242  
QUADRUPLE BUS TRANSCEIVERS  
WITH 3-STATE OUTPUTS  
SDFS062A – D2932, MARCH 1987 – REVISED OCTOBER 1993  
SN54F242 . . . J PACKAGE  
SN74F242 . . . D OR N PACKAGE  
(TOP VIEW)  
• Asynchronous Communication Between  
Data Buses  
• Local Bus-Latch Capability  
• Inverting Logic  
• Package Options Include Plastic  
Small-Outline Packages, Ceramic Chip  
Carriers, and Standard Plastic and Ceramic  
300-mil DIPs  
OEAB  
NC  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
OEBA  
NC  
B1  
A1  
A2  
A3  
B2  
A4  
B3  
description  
GND  
B4  
8
These quadruple bus transceivers are designed  
for asynchronous communications between data  
buses. Thecontrolfunctionimplementationallows  
for maximum flexibility in timing. These devices  
allow data transmission from the A bus to the  
B bus or from the B bus to the A bus depending  
upon the logic levels at the output-enable (OEBA  
and OEAB) inputs. The output-enable inputs can  
be used to disable the device so that the buses are  
effectively isolated.  
SN54F242 . . . FK PACKAGE  
(TOP VIEW)  
3
2
1
20 19  
18  
NC  
NC  
B1  
A1  
NC  
A2  
4
5
6
7
8
17  
16  
15  
14  
NC  
B2  
NC  
A3  
The dual-enable configuration gives the  
quadruple bus transceivers the capability to store  
data by simultaneous enabling of OEBA and  
OEAB. Each output reinforces its input in this  
transceiverconfiguration. Thus, whenbothcontrol  
inputs are enabled and all other data sources to  
the two sets of bus lines are at high impedance,  
both sets of bus lines (eight in all) remain at their  
states. The 4-bit codes appearing on the two sets  
of buses will be complementary for the ′F242.  
9 10 11 12 13  
NC – No internal connection  
The SN54F242 is characterized for operation over the full military temperature range of –55°C to 125°C. The  
SN74F242 is characterized for operation from 0°C to 70°C.  
FUNCTION TABLE  
INPUTS  
FUNCTION  
OEAB  
OEBA  
L
H
H
L
H
L
A to B  
B to A  
Isolation  
Latch A and B  
(A = B)  
L
H
Copyright 1993, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
2–1  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
12345

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