Datasheet > SMJ44400JD

SMJ44400JD

更新时间： 2024-01-19 03:37:39

品牌	Logo	应用领域
AUSTIN		存储动态存储器
页数	文件大小	规格书
21页	352K
描述
1M x 4 DRAM DYNAMIC RANDOM-ACCESS MEMORY

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

SMJ44400JD 数据手册

DRAM

SMJ44400

Austin Semiconductor, Inc.

1M x 4 DRAM

PIN ASSIGNMENT

(Top View)

DYNAMIC RANDOM-ACCESS

MEMORY

20-Pin DIP (JD)

20-Pin Flatpack (HR)

(400 MIL)

AVAILABLE AS MILITARY

SPECIFICATIONS

• SMD 5962-90847

• MIL-STD-883

DQ1

DQ2

RAS\

Vss

DQ4

DQ3

CAS\

OE\

FEATURES

• Organized 1,048,576 x 4

• Single +5V ±10% power supply

• Enhanced Page-Mode operation for faster memory access

P Higher data bandwidth than conventional page-mode

parts

P Random Single-Bit Access within a row with a column

address

Vcc 10

Pin Name

Function

A0 - A9 Address Inputs

CAS\

Column-Address Strobe

DQ1 - DQ4 Data Inputs/Outputs

• CAS\-Before-RAS\ (CBR) Refresh

• Long Refresh period: 1024-cycle Refresh in 16ms (Max)

• 3-State unlatched Output

• Low Power Dissipation

• All Inputs/Outputs and Clocks are TTL Compatible

• Processing to MIL-STD-883, Class B available

OE\

RAS\

Vcc

Vss

Output Enable

Row-Address Strobe

Write Enable

5V Supply

Ground

OPTIONS

• Timing

80ns access

100ns access

120ns access

MARKING

The SMJ44400 is offered in a 400-mil, 20-pin ceramic

side-brazed dual-in-line package (JD suffix) and a 20-pin

ceramic flatpack (HR suffix) that are characterized for

operation from -55°C to +125°C.

-80

-10

-12

OPERATION

• Package(s)

Ceramic DIP (400mils)

Ceramic Flatpack

No. 113

No. 308

Enhanced Page Mode

Enhanced page-mode operation allows faster memory

access by keeping the same row address while selecting

random column addresses. The time for row-address setup

and hold and address multiplex is eliminated. The maximum

number of columns that can be accessed is determined by the

maximum RAS\ low time and the CAS\ page cycle time used.

With minimum CAS\ page cycle time, all 1024 columns

specified by column addresses A0 through A9 can be accessed

without intervening RAS\ cycles.

• Operating Temperature Ranges

Military (-55^oC to +125^oC)

GENERAL DESCRIPTION

The SMJ44400 is a series of 4,194,304-bit dynamic ran-

dom-access memories (DRAMs), organized as 1,048,576

words of four bits each. This series employs state-of-the-art

technology for high performance, reliability, and low-power

operation.

The SMJ44400 features maximum row access times of

80ns, 100ns, and 120ns. Maximum power dissipation is as

low as 360mW operating and 22mW standby.

All inputs and outputs, including clocks, are compatible

with Series 54 TTL. All addressses and data-in lines are latched

on-chip to simplify system design. Data out is unlatched to

allow greater system flexibility.

Unlike conventional page-mode DRAMs, the column-

address buffers in this device are activated on the

For more products and information

please visit our web site at

www.austinsemiconductor.com

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

SMJ44400

Rev. 2.0 10/01

12 3 4 5 6 7...21

中文翻译

下载PDF

与SMJ44400JD相关器件

型号	品牌	获取价格	描述	数据表
SMJ44400JD-10/IT	MICROSS	获取价格	EDO DRAM, 1MX4, 100ns, CMOS, CDIP20, 0.400 INCH, SIDE BRAZED, CERAMIC, DIP-20
SMJ44400JD-10/XT	MICROSS	获取价格	EDO DRAM, 1MX4, 100ns, CMOS, CDIP20, 0.400 INCH, SIDE BRAZED, CERAMIC, DIP-20
SMJ44400JD-12/883C	MICROSS	获取价格	EDO DRAM, 1MX4, 120ns, CMOS, CDIP20, 0.400 INCH, SIDE BRAZED, CERAMIC, DIP-20
SMJ44400JD-12/XT	MICROSS	获取价格	EDO DRAM, 1MX4, 120ns, CMOS, CDIP20, 0.400 INCH, SIDE BRAZED, CERAMIC, DIP-20
SMJ44400JD-8/XT	MICROSS	获取价格	EDO DRAM, 1MX4, 80ns, CMOS, CDIP20, 0.400 INCH, SIDE BRAZED, CERAMIC, DIP-20
SMJ4461-15JDL	TI	获取价格	64KX4 VIDEO DRAM, 150ns, CDIP24, 0.400 INCH, HERMETIC SEALED, SIDE BRAZED, CERAMIC, DIP-24
SMJ4461-15JDS	TI	获取价格	64KX4 VIDEO DRAM, 150ns, CDIP24, 0.400 INCH, HERMETIC SEALED, SIDE BRAZED, CERAMIC, DIP-24
SMJ4464-12FVL	TI	获取价格	64KX4 PAGE MODE DRAM, 120ns, CQCC18, CERAMIC, LCC-18
SMJ4464-12FVS	TI	获取价格	64KX4 PAGE MODE DRAM, 120ns, CQCC18, CERAMIC, LCC-18
SMJ4464-12JDL	ROCHESTER	获取价格	Page Mode DRAM, 64KX4, 120ns, NMOS, CDIP18, 0.300 INCH, HERMETIC SEALED, SIDE BRAZED, CERA

与SMJ44400JD相关文章

MBRS340T3G手册解读：参数说明、产品特性及应用
2024-06-28

1
PMOS管背靠背连接：串联还是并联？
2024-06-28

1
高压电解电容的分类与选型策略
2024-06-28

2
数码管：基本概念、分类、技术发展及市场趋势
2024-06-27

6

产品中心

服务支持

精选活动

关于我们

帮助中心

SMJ44400JD

SMJ44400JD 数据手册

与SMJ44400JD相关器件

与SMJ44400JD相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

SMJ44400JD

SMJ44400JD 数据手册

与SMJ44400JD相关器件

与SMJ44400JD相关文章

您还可以找

您在本页遇到什么问题？