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SMJ44C251

更新时间: 2024-11-24 21:55:47
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
53页 947K
描述
262144 BY 4-BIT MULTIPORT VIDEO RAM

SMJ44C251 数据手册

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SMJ44C251B  
262144 BY 4-BIT  
MULTIPORT VIDEO RAM  
SGMS058A – MARCH 1995 – REVISED JUNE 1995  
Military Operating Temperature Range  
Enhanced Page-Mode Operation for Faster  
Access  
– 55°C to 125°C  
Performance Ranges:  
CAS-Before-RAS (CBR) and Hidden  
Refresh Modes  
ACCESS  
TIME  
ACCESS ACCESS ACCESS  
TIME  
TIME  
TIME  
SERIAL  
ENABLE  
(MAX)  
All Inputs/Outputs and Clocks Are TTL  
Compatible  
ROW  
COLUMN SERIAL  
ADDRESS ENABLE DATA  
(MAX) (MAX) (MAX)  
Long Refresh Period  
Every 8 ms (Max)  
t
t
t
t
a(SE)  
20 ns  
a(R)  
a(C)  
a(SQ)  
Up to 33-MHz Uninterrupted Serial-Data  
Streams  
’44C251B-10 100 ns  
’44C251B-12 120 ns  
25 ns  
30 ns  
30 ns  
35 ns  
25 ns  
3-State Serial I/Os Allow Easy Multiplexing  
of Video-Data Streams  
Class B High-Reliability Processing  
DRAM: 262144 Words × 4 Bits  
SAM: 512 Words × 4 Bits  
512 Selectable Serial-Register Starting  
Locations  
Single 5-V Power Supply (±10% Tolerance)  
Packaging:  
– 28-Pin J-Leaded Ceramic Chip Carrier  
Package (HJ Suffix)  
– 28-Pin Leadless Ceramic Chip Carrier  
Package (HM Suffix)  
– 28-Pin Ceramic Sidebrazed DIP  
(JD Suffix)  
Dual Port AccessibilitySimultaneous and  
Asynchronous Access From the DRAM and  
SAM Ports  
Bidirectional-Data-Transfer Function  
Between the DRAM and the Serial-Data  
Register  
4 × 4 Block-Write Feature for Fast Area Fill  
Operations; As Many as Four Memory  
Address Locations Written per Cycle From  
an On-Chip Color Register  
– 28-Pin Zig-Zag In-Line (ZIP), Ceramic  
Package (SV Suffix)  
Split Serial-Data Register for Simplified  
Real-Time Register Reload  
Write-Per-Bit Feature for Selective Write to  
Each RAM I/O; Two Write-Per-Bit Modes to  
Simplify System Design  
description  
PIN NOMENCLATURE  
A0A8  
CAS  
DQ0DQ3  
SE  
RAS  
SC  
SDQ0SDQ3 Serial Data In-Out  
TRG  
W
DSF  
QSF  
Address Inputs  
Column Enable  
DRAM Data In-Out/Write-Mask Bit  
Serial Enable  
Row Enable  
The SMJ44C251B multiport video RAM is a  
high-speed, dual-ported memory device. It  
consists of a dynamic random-access memory  
(DRAM) organized as 262144 words of 4 bits  
each interfaced to a serial-data register or  
serial-access memory (SAM) organized as 512  
words of 4 bits each. The SMJ44C251B supports  
three types of operation: random access to and  
from the DRAM, serial access to and from the  
serial register, and bidirectional transfer of data  
between any row in the DRAM and the serial  
register. Except during transfer operations, the  
SMJ44C251B can be accessed simultaneously  
and asynchronously from the DRAM and SAM  
ports.  
Serial Data Clock  
Transfer Register/Q Output Enable  
Write-Mask Select/Write Enable  
Special Function Select  
Split-Register Activity Status  
5-V Supply  
V
V
SS  
GND  
CC  
Ground  
Ground (Important: Not connected  
to internal V  
)
SS  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1995, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443  

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