SMJ44400
1 048 576 BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS041D – JANUARY 1991 – REVISED JUNE 1995
JDB OR HR PACKAGES
(TOP VIEW)
HL PACKAGE
(TOP VIEW)
Processed to MIL-STD-883, Class B
Organization . . . 1 048 576 × 4
Single 5-V Power Supply (±10% Tolerance)
Performance Ranges:
1
2
3
4
5
26
25
24
23
22
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
DQ1
DQ2
W
V
SS
DQ1
DQ2
W
RAS
A9
A0
A1
A2
V
SS
DQ4
DQ3
CAS
OE
DQ4
DQ3
CAS
OE
A8
A7
A6
A5
A4
ACCESS ACCESS ACCESS
TIME TIME TIME OR WRITE
(t (t
READ
RAS
A9
)
)
(t
AA
)
CYCLE
(MIN)
RAC CAC
(MAX)
80 ns
(MAX)
20 ns
25 ns
30 ns
(MAX)
40 ns
45 ns
55 ns
SMJ44400-80
SMJ44400-10
SMJ44400-12
150 ns
180 ns
210 ns
9
18
17
16
A8
A7
A6
A0
A1
A2
A3
100 ns
120 ns
10
11
12
13
A3
V
CC
Enhanced Page-Mode Operation for Faster
Memory Access
– Higher Data Bandwidth Than
Conventional Page-Mode Parts
– Random Single-Bit Access Within a Row
With a Column Address
15 A5
14
A4
V
CC
SV PACKAGE
(TOP VIEW)
OE
DQ3
1
CAS-Before-RAS (CBR) Refresh
CAS
2
3
Long Refresh Period
DQ4
DQ1
W
A9
A1
A3
A4
A6
A8
4
V
5
SS
1024-Cycle Refresh in 16 ms (Max)
6
DQ2
RAS
AO
7
8
3-State Unlatched Output
Low Power Dissipation
9
10
11
12
13
14
15
16
17
18
19
20
A2
All Inputs/Outputs and Clocks are TTL
Compatible
V
CC
A5
A7
Packaging Options:
– 20-Pin, 300-Mil Ceramic Side-Brazed DIP
(JDB suffix)
– 20-Pin Ceramic Flatpack (HR Suffix)
– 20-Pad, 350 × 675 Ceramic Chip Carrier
(HL suffix)
– 20-Pin Ceramic ZIP (SV suffix)
– Additional Package Options Planned
PIN NOMENCLATURE
A0–A9
CAS
Address Inputs
Column-Address Strobe
Data In/Data Out
Output Enable
Row-Address Strobe
Write Enable
DQ1–DQ4
OE
RAS
W
Military Temperature Range
–55 to 125°C
V
CC
V
SS
5-V Supply
Ground
description
TheSMJ44400isaseriesof4194304-bitdynamicrandom-accessmemories(DRAMs), organizedas1048576
words of four bits each. This series employs state-of-the-art technology for high performance, reliability, and
low–power operation.
The SMJ44400 features maximum row access times of 80 ns, 100 ns, and 120 ns. Maximum power dissipation
is as low as 360 mW operating and 22 mW standby.
All inputs and outputs, including clocks, are compatible with Series 54 TTL. All addresses and data-in lines are
latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
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