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SL23EP05SC-1T PDF预览

SL23EP05SC-1T

更新时间: 2024-11-02 03:04:31
品牌 Logo 应用领域
SPECTRALINEAR /
页数 文件大小 规格书
11页 151K
描述
Low Jitter and Skew 10 to 220MHz Zero Delay Buffer (ZDB)

SL23EP05SC-1T 数据手册

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SL23EP05  

Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer (ZDB)  
Key Features  
Description  
x
x
10 to 220 MHz operating frequency range  
Low output clock jitter:  
The SL23EP05 is a low skew, low jitter and low power Zero  
Delay Buffer (ZDB) designed to produce up to five (5) clock  
outputs from one (1) reference input clock for high speed  
clock distribution applications. The product has an on-chip  
PLL which locks to the input clock at CLKIN and receives its  
feedback internally from the CLKOUT pin.  


20 ps-typ cycle-to-cycle jitter  
15 ps-typ period jitter  
x
x
x
x
Low output-to-output skew: 30 ps-typ  
Low product-to-product skew: 60 ps-typ  
Wide 2.5 V to 3.3 V power supply range  
Low power dissipation:  
The SL23EP05 is available with two (2) drive strength  
versions called -1 and -1H. The -1 is the standard-drive  
version and -1H is the high-drive version.  


16 mA-max at 66 MHz and VDD=3.3 V  
14 mA-max at 66 MHz and VDD=2.5V  
The SL23EP05 high-drive version operates up to 220MHz  
and 200MHz at 3.3V and 2.5V power supplies respectively.  
The standard drive version -1 operates up to 167MHz and  
133MHz at 3.3V and 2.5V respectively.  
x
x
x
x
x
One input drives 5 outputs organized as 4+1  
SpreadThru™ PLL that allows use of SSCG  
Standard and High-Drive options  
The SL23EP05 enter into Power Down (PD) mode if the  
input at CLKIN is less then 2.0MHz or there is no rising  
edge. In this state all five (5) outputs are tri-stated and the  
PLL is turned off leading to less than 10ȝA of power supply  
current draw.  
Available in 150 mil 8-pin SOIC package  
Available in Commercial and Industrial grades  
Applications  
x
x
x
x
x
Printers and MFPs  
Benefits  
Digital Copiers  
x
x
Up to five (5) distribution of input clock  
PCs and Work Stations  
Routers, Switchers and Servers  
Digital Embeded Systems  
Standard and High-Dirive levels to control impedance  
level, frequency range and EMI  
x
x
Low power dissipation, jitter and skew  
Low cost  
Block Diagram  
Rev 1.0, May 21, 2007  
Page 1 of 11  
2200 Laurelwood Road, Santa Clara, CA 95054 Tel: (408) 855-0555 Fax: (408) 855-0550 www.SpectraLinear.com  

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