Datasheet > SL23EP08

SL23EP08

更新时间： 2024-01-21 09:21:46

品牌	Logo	应用领域
芯科 - SILICON		/
页数	文件大小	规格书
15页	227K
描述
Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer

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数据手册

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SL23EP08 数据手册

SL23EP08

Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer (ZDB)

Key Features

Description

•

10 to 220 MHz operating frequency range

Low output clock skew: 45ps-typ

Low output clock jitter:

The SL23EP08 is a low skew, low jitter and low power Zero

Delay Buffer (ZDB) designed to produce up to nine (9) clock

outputs from one (1) reference input clock, for high speed

clock distribution applications.



25 ps-typ cycle-to-cycle jitter

15 ps-typ period jitter

The product has an on-chip PLL and a feedback pin (FBK)

which can be used to obtain feedback from any one of the

output clocks. The SL23EP08 has two (2) clock driver banks

each with four (4) clock outputs. These outputs are controlled

by two (2) select input pins S1 and S2. When only four (4)

outputs are needed, four (4) bank-B output clock buffers can

be tri-stated to reduce power dissipation and jitter. The select

inputs can also be used to tri-state both banks A and B or

drive them directly from the input bypassing the PLL and

making the product behave like a Non-Zero Delay Buffer

(NZDB). The product also offers various 1X, 2X and 4X

frequency options at the output clocks. Refer to the “Product

Configuration Table” for the details.

•

Low part-to-part output skew: 90 ps-typ

Wide 2.5 V to 3.3 V power supply range

Low power dissipation:



20 mA-max at 66 MHz and VDD=3.3 V

18 mA-max at 66 MHz and VDD=2.5V

•

One input drives 8 outputs

Multiple configurations and drive options

Select mode to bypass PLL or tri-state outputs

SpreadThru™ PLL that allows use of SSCG

Available in 16-pin SOIC and TSSOP packages

Available in Commercial and Industrial grades

The high-drive version operates up to 220MHz and 200MHz at

3.3V and 2.5V power supplies respectively.

Applications

Benefits

•

Printers, MFPs and Digital Copiers

•

Up to eight (8) distribution of input clock

PCs and Work Stations

Standard and High-Dirive levels to control impedance

level, frequency range and EMI

Routers, Switchers and Servers

Datacom and Telecom

•

Low power dissipation, jitter and skew

Low cost

High-SpeedDigital Embeded Systems

Block Diagram

Low Power and

Low Jitter

PLL

(Divider for -3 and -4 only)

CLKIN

MUX

FBK

(Divider for -5H only)

CLKA1

CLKA2

CLKA3

CLKA4

Input Selection

Decoding Logic

(Divider for -2 and -3 only)

CLKB1

CLKB2

CLKB3

CLKB4

VDD

GND

Rev 1.0, May 18, 2006

2400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500

Page 1 of 15

www.silabs.com

1+(512) 416-9669

12 3 4 5 6 7...15

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与SL23EP08相关器件

型号	品牌	获取价格	描述	数据表
SL23EP08SC-1	SPECTRALINEAR	获取价格	Low Jitter and Skew 10 to 220MHz Zero Delay Buffer (ZDB)
SL23EP08SC-1	SILICON	获取价格	PLL Based Clock Driver, 23EP Series, 4 True Output(s), 0 Inverted Output(s), PDSO16, SOIC-
SL23EP08SC-1H	SPECTRALINEAR	获取价格	Low Jitter and Skew 10 to 220MHz Zero Delay Buffer (ZDB)
SL23EP08SC-1H	SILICON	获取价格	Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer
SL23EP08SC-1HT	SPECTRALINEAR	获取价格	Low Jitter and Skew 10 to 220MHz Zero Delay Buffer (ZDB)
SL23EP08SC-1HT	SILICON	获取价格	Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer
SL23EP08SC-1T	SPECTRALINEAR	获取价格	Low Jitter and Skew 10 to 220MHz Zero Delay Buffer (ZDB)
SL23EP08SC-1T	SILICON	获取价格	PLL Based Clock Driver, 23EP Series, 4 True Output(s), 0 Inverted Output(s), PDSO16, SOIC-
SL23EP08SC-2	SPECTRALINEAR	获取价格	Low Jitter and Skew 10 to 220MHz Zero Delay Buffer (ZDB)
SL23EP08SC-2	SILICON	获取价格	PLL Based Clock Driver, 23EP Series, 4 True Output(s), 0 Inverted Output(s), PDSO16, SOIC-

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