Datasheet > SL23EP08SC-2T

SL23EP08SC-2T

更新时间： 2024-11-02 04:04:23

品牌	Logo	应用领域
SPECTRALINEAR		/
页数	文件大小	规格书
18页	174K
描述
Low Jitter and Skew 10 to 220MHz Zero Delay Buffer (ZDB)

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SL23EP08SC-2T 数据手册

Preliminary

SL23EP08

Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer (ZDB)

Key Features

Description

The SL23EP08 is a low skew, low jitter and low power

Zero Delay Buffer (ZDB) designed to produce up to eight

(8) clock outputs from one (1) reference input clock, for

high speed clock distribution applications.

10 to 220 MHz operating frequency range

Low output clock skew: 70ps-typ

Low output clock Jitter: 50 ps-typ

- 50 ps-typ at 166MHz, CL=15pF and VDD=3.3V

- 75 ps-typ at 166MHz, CL=15pF and VDD=2.5V

Low part-to-part output skew: 150 ps-typ

3.3V to 2.5V power supply range

The product has an on-chip PLL and a feedback pin (FBK)

which can be used to obtain feedback from any one of the

output clocks. The SL23EP08 has two (2) clock driver

banks each with four (4) clock outputs. These outputs are

controlled by two (2) select input pins S1 and S2. When

only four (4) outputs are needed, bank-B output clock

buffers can be tri-stated to reduce power dissipation and

jitter. The select inputs can also be used to tri-state both

banks A and B or drive them directly from the input

bypassing the PLL and making the product behave like a

Non-Zero Delay Buffer (NZDB). The SL23EP08 offers

various X/2,1X, 2X and 4x frequency options at the output

clocks. Refer to the “Product Configuration Table” for the

details.

Low power dissipation:

- 22 mA-typ at 66MHz and VDD=3.3V

- 20 mA-typ at 66MHz and VDD=2.5V

One input drives 8 outputs

Multiple configurations and drive options

Select mode to bypass PLL or tri-state outputs

SpreadThru™ PLL that allows use of SSCG

Available in 16-pin SOIC and TSSOP packages

Available in Commercial and Industrial grades

The SL23EP08-1H, -2H and 5H versions operates up to

220 MHz and SL23EP08-1, -2, -3 and -4 versions operate

up to 133 MHz with CL=15pF output load.

Applications

Benefits

Printers, MFPs and Digital Copiers

PCs and Work Stations

Up to eight (8) distribution of input clock

Routers, Switchers and Servers

Datacom and Telecom

Standard and High-Dirive levels to control

impedance level, frequency range and EMI

Low skew, jitter and power dissipation

High-Speed Digital Embeded Systems

Block Diagram

Low Power and

Low Jitter

PLL

(Divider for -3 and -4)

CLKIN

MUX

FBK

(Divider for -5H only)

CLKA1

CLKA2

CLKA3

CLKA4

Input Selection

Decoding Logic

(Divider for -2, -2H and -3)

CLKB1

CLKB2

CLKB3

CLKB4

VDD

GND

Rev 1.4, May 28, 2007

Page 1 of 18

2200 Laurelwood Road, Santa Clara, CA 95054 Tel: (408) 855-0555 Fax: (408) 855-0550 www.SpectraLinear.com

12 3 4 5 6 7...18

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与SL23EP08SC-2T相关器件

型号	品牌	获取价格	描述	数据表
SL23EP08SC-3	SILICON	获取价格	Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer
SL23EP08SC-3T	SILICON	获取价格	Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer
SL23EP08SC-4	SPECTRALINEAR	获取价格	Low Jitter and Skew 10 to 220MHz Zero Delay Buffer (ZDB)
SL23EP08SC-4	SILICON	获取价格	PLL Based Clock Driver, 23EP Series, 4 True Output(s), 0 Inverted Output(s), PDSO16, 0.150
SL23EP08SC-4T	SPECTRALINEAR	获取价格	Low Jitter and Skew 10 to 220MHz Zero Delay Buffer (ZDB)
SL23EP08SC-4T	SILICON	获取价格	PLL Based Clock Driver, 23EP Series, 4 True Output(s), 0 Inverted Output(s), PDSO16, SOIC-
SL23EP08SC-5H	SPECTRALINEAR	获取价格	Low Jitter and Skew 10 to 220MHz Zero Delay Buffer (ZDB)
SL23EP08SC-5H	SILICON	获取价格	PLL Based Clock Driver, 23EP Series, 4 True Output(s), 0 Inverted Output(s), PDSO16, 0.150
SL23EP08SC-5HT	SILICON	获取价格	Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer
SL23EP08SC-5HT	SPECTRALINEAR	获取价格	Low Jitter and Skew 10 to 220MHz Zero Delay Buffer (ZDB)

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