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SL23EP08SC-1T PDF预览

SL23EP08SC-1T

更新时间: 2024-01-22 18:46:40
品牌 Logo 应用领域
芯科 - SILICON 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
18页 496K
描述
PLL Based Clock Driver, 23EP Series, 4 True Output(s), 0 Inverted Output(s), PDSO16, SOIC-16

SL23EP08SC-1T 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP,针数:16
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.62其他特性:ALSO OPERATES WITH 3.3V SUPPLY
系列:23EP输入调节:MUX
JESD-30 代码:R-PDSO-G16长度:4.889 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER功能数量:2
反相输出次数:端子数量:16
实输出次数:4最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.5 ns座面最大高度:1.727 mm
最大供电电压 (Vsup):2.7 V最小供电电压 (Vsup):2.3 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3.8989 mm
最小 fmax:220 MHzBase Number Matches:1

SL23EP08SC-1T 数据手册

 浏览型号SL23EP08SC-1T的Datasheet PDF文件第2页浏览型号SL23EP08SC-1T的Datasheet PDF文件第3页浏览型号SL23EP08SC-1T的Datasheet PDF文件第4页浏览型号SL23EP08SC-1T的Datasheet PDF文件第5页浏览型号SL23EP08SC-1T的Datasheet PDF文件第6页浏览型号SL23EP08SC-1T的Datasheet PDF文件第7页 
SL23EP08  
Not Recommended for New Designs  
Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer (ZDB)  
Key Features  
Description  
10 to 220 MHz operating frequency range  
The SL23EP08 is a low skew, low jittew power Zero  
Delay Buffer (ZDB) designed to pce uto nine (9) clock  
outputs from one (1) reference inloc, for high speed clock  
distribution applications.  
Low output clock skew: 45ps-typ  
Low output clock jitter:  
25 ps-typ cycle-to-cycle jitter  
15 ps-typ period jitter  
The product has an on-L and a feedback pin (FBK)  
which can be used to obedback from any one of the  
output clocks. The SL2EP08 has two (2) clock driver banks  
each with four (4) lock outputs. These outputs are controlled  
by two (2) select input pins S1 and S2. When only our (4)  
outputs are d, four (4) bank-B output clock buffers can be  
tri-stated to ducpower dissipation nd jittr. The select  
inputs can also be used to tri-state both banks A and B or drive  
them directy from the input bypasshe PL and making the  
podut behave like a Non-Zero Buffer (NZDB). The  
poduct lso offers various 1X2X frquency options at  
the output clocks. Refer to the Product Configuration Table”  
for the details.  
Low part-to-part output skew: 90 ps-typ  
Wide 2.5 V to 3.3 V power supply range  
Low power dissipation:  
20 mA-max at 66 MHz and VDD=3.3 V  
18 mA-max at 66 MHz and VDD=2.5V  
One input drives 8 outputs  
Multiple configurations and drive options  
Select mode to bypass PLL or tri-state outputs  
SpreadThru™ PLL that allows use of SSCG  
Available in 16-pin SOIC and TSSOP packages  
Available in Commercial and Industrial grade
The high-drive version operates up to 220MHz and 200MHz at  
3.3V and 2.5V poupplies respectively.  
Applications  
Benefi
Printers, MFPs and Digital Copiers  
8) distribution of input clock  
PCs and Work Stations  
Std High-Dirive levels to control impedance  
level, uency range and EMI  
Routers, Switchers and Servers  
Datacom and Telecom  
Low power dissipation, jitter and skew  
Low cost  
High-SpeedDigital EmbeSysems  
Block Diagra
/2  
Lwer nd  
w Jitte
PLL  
(Divider for -3 and -4 only
/2  
CLKIN  
MUX  
FBK  
(Divider fnly)  
CLKA1  
CLKA2  
CLKA3  
CLKA4  
2  
S1  
Input Selection  
Decoding Logic  
/2  
(Divider for -2 and -3 only)  
CLKB1  
CLKB2  
CLKB3  
CLKB4  
2
2
VDD  
GND  
Rev 1.1, Feb 11, 2016  
2400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500  
Page 1 of 17  
www.silabs.com  
1+(512) 416-9669  

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