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SL23EP05SI-1H PDF预览

SL23EP05SI-1H

更新时间: 2024-11-03 02:57:47
品牌 Logo 应用领域
芯科 - SILICON /
页数 文件大小 规格书
15页 284K
描述
LOW JITTER AND SKEW 10 TO 220 MHZ ZERO DELAY BUFFER

SL23EP05SI-1H 数据手册

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SL23EP05  
LOW JITTER AND SKEW 10 TO 220 MHZ ZERO DELAY  
BUFFER (ZDB)  
Features  
10 to 220 MHz operating  
Low power dissipation:  
frequency range  
16 mA-max at 66 MHz and  
VDD = 3.3 V  
Low output clock jitter:  
14 mA-max at 66 MHz and  
VDD = 2.5 V  
50 ps-typ cycle-to-cycle jitter  
20 ps-typ period jitter  
Low output-to-output skew:  
30 ps-typ  
One input drives five outputs  
organized as 4+1  
SpreadThru™ PLL that allows  
Low product-to-product skew:  
use of SSCG  
60 ps-typ  
Standard and High-Drive options  
Wide 2.5 V to 3.3 V power supply  
Available in 8 pin SOIC and  
range  
TSSOP packages  
Ordering Information:  
Available in Commercial and  
See page 14.  
Industrial grades  
Applications  
Pin Assignments  
SL23EP05  
Printers and MFPs  
Digital Copiers  
Routers, Switchers and Servers  
Digital Embedded Systems  
PCs and Work Stations  
Benefits  
Up to five distribution of input  
Low power dissipation, jitter and  
clock  
skew  
Standard and High-Drive levels Low cost  
to control impedance level,  
frequency range and EMI  
Description  
Patents pending  
The SL23EP05 is a low skew, low jitter, and low power Zero Delay Buffer  
(ZDB) designed to produce up to five clock outputs from one reference input  
clock for high speed clock distribution applications. The product has an on-  
chip PLL which locks to the input clock at CLKIN and receives its feedback  
internally from the CLKOUT pin.  
The SL23EP05 is available with two drive strength versions called –1 and  
–1H. The –1 is the standard-drive version and –1H is the high-drive version.  
The SL23EP05 high-drive version operates up to 220 MHz and 180 MHz at  
3.3 V and 2.5 V power supplies, respectively. The standard drive version –1  
operates up to 200 MHz and 167 MHz at 3.3 V and 2.5 V, respectively.  
The SL23EP05 enter into Power Down (PD) mode if the input at CLKIN is  
less then 2.0 MHz or there is no rising edge. In this state all five outputs are  
tri-stated and the PLL is turned off leading to less than 10 μA of power  
supply current draw.  
Rev. 2.2 5/15  
Copyright © 2015 by Silicon Laboratories  
SL23EP05  

SL23EP05SI-1H 替代型号

型号 品牌 替代类型 描述 数据表
SL23EP05SC-1HT SILICON

类似代替

LOW JITTER AND SKEW 10 TO 220 MHZ ZERO DELAY BUFFER
SL23EP05SC-1 SILICON

类似代替

LOW JITTER AND SKEW 10 TO 220 MHZ ZERO DELAY BUFFER
CY23EP05SXC-1H CYPRESS

功能相似

2.5V or 3.3V,10- 220 MHz, Low Jitter, 5 Output Zero Delay Buffer

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