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SK10E151 PDF预览

SK10E151

更新时间: 2024-09-15 22:43:11
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商升特 - SEMTECH /
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描述
6-Bit D Register

SK10E151 数据手册

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SK10/100E151  
6-Bit D Register  
HIGH-PERꢀORMANCE PRODUCTS  
ꢀeatures  
Description  
• 1100 MHz Toggle Frequency  
• Extended 100E VEE Range of –4.2V to –5.46V  
• Differential Outputs  
• Asynchronous Master Reset  
• Dual Clocks  
The SK10/100E151 offers 6 edge-triggered, high-speed,  
master-slave D-type flip-flops with differential outputs,  
designed for use in new high-performance ECL systems.  
This device is fully compatible with MC10E151 and  
MC100E151. The two external clock signals (CLK1, CLK2)  
are gated through a logical OR operation before use as  
clocking control for the flip-flops. Data is clocked into  
the flip-flops on the rising edge of either CLK1 or CLK2  
(or both). When both CLK1 and CLK2 are at a logic  
LOW, data enters the master and is transferred to the  
slave when either CLK or CLK2 (or both) go HIGH.  
• Internal 75KInput Pull-Down Resistors  
• ESD Protection of >4000V  
• Fully Compatible with MC10E/100E151  
• Specified Over Industrial Temperature Range:  
o
o
–40 C to +85 C  
• Available in 28-Pin PLCC Package  
The MR (Master Reset) signal operates asynchronously  
to make all Q outputs go to a logic LOW.  
PIN Description  
Pin  
D0–D5  
CLK1, CLK2  
MR  
ꢀunction  
ꢀunctional Block Diagram  
Data Inputs  
Clock Inputs  
Q0  
D0  
D1  
D2  
D3  
D4  
D5  
D
D
D
D
D
D
Master Reset  
True Outputs  
Q0*  
R
R
R
R
R
R
Q0–Q5  
Q0*–Q5*  
VCC0  
Q1  
Inverting Outputs  
VCC to Output  
Q1*  
Q2  
Q2*  
Q3  
Q3*  
Q4  
D5  
D4  
D3  
VEE  
D2  
D1  
D0  
26  
27  
28  
1
18  
17  
16  
15  
14  
13  
12  
Q4*  
Q4  
Q4*  
VCC  
Q3*  
Q3  
PLCC  
TOP VIEW  
Q5  
2
Q5*  
3
Q2*  
Q2  
4
CLK1  
CLK2  
MR  
www.semtech.com  
Revision 1/ꢀebruary 13, 2001  
1

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