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SK10E445PJT

更新时间： 2024-11-05 22:43:11
品牌 Logo 应用领域
商升特 - SEMTECH 转换器移位寄存器触发器逻辑集成电路
页数 文件大小 规格书
8页 171K
描述
4-Bit Serial/Parallel Converter

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中文翻译

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SK10E445PJT 技术参数

生命周期：Obsolete零件包装代码：QLCC
包装说明：QCCJ,针数：28
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.84Is Samacsys：N
计数方向：RIGHT系列：10E
JESD-30 代码：S-PQCC-J28长度：11.505 mm
逻辑集成电路类型：SERIAL IN PARALLEL OUT位数：4
功能数量：1端子数量：28
最高工作温度：85 °C最低工作温度：
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装形状：SQUARE
封装形式：CHIP CARRIER传播延迟（tpd）：1.8 ns
认证状态：Not Qualified座面最大高度：4.57 mm
表面贴装：YES技术：ECL
温度等级：OTHER端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
触发器类型：POSITIVE EDGE宽度：11.505 mm
Base Number Matches：1

SK10E445PJT 数据手册

 浏览型号SK10E445PJT的Datasheet PDF文件第2页浏览型号SK10E445PJT的Datasheet PDF文件第3页浏览型号SK10E445PJT的Datasheet PDF文件第4页浏览型号SK10E445PJT的Datasheet PDF文件第5页浏览型号SK10E445PJT的Datasheet PDF文件第6页浏览型号SK10E445PJT的Datasheet PDF文件第7页 
SK10/100E445  
4-Bit Serial/Parallel Converter  
HIGH-PERꢀORMANCE PRODUCTS  
ꢀeatures  
Description  
The SK10/100E445 is an integrated 4-bit serial-to-  
parallel data converter. The device is designed to operate  
for NRZ data rates of up to 2.0 Gb/s. The chip generates  
a divide by 4 and a divide by 8 clock for both 4-bit  
conversion and a two chip 8-bit conversion function. The  
conversion sequence was chosen to convert the first  
serial bit to Q0, the second to Q1, etc.  
• On-Chip Clock ÷ 4 and ÷8  
• 2.0 Gb/s Data Rate Capability  
• Differential Clock and Serial Inputs  
• V Output for Single-Ended Input Applications  
BB  
• Asynchronous Data Synchronization  
• Mode Select to Expand to 8-Bits  
• Internal 75 kΩ Input Pulldown Resistors  
• ESD Protection of >4000V  
• Extended 100E VEE Range of –4.2V to –5.46V  
• Fully Compatible with MC10/100E445  
• Available in 28-Pin PLCC Package  
Two selectable serial inputs provide a loopback capability  
for testing purposes when the device is used in  
conjunction with the R446 parallel to serial converter.  
The start bit for conversion can be moved using the SYNC  
input. A single pulse applied asynchronously for at least  
two input clock cycles shifts the start bit for conversion  
from Qn to Qn–1. For each additional shift required, an  
additional pulse must be applied to the SYNC input.  
Asserting the SYNC input will force the internal clock  
dividers to “swallow” a clock pulse, effectively shifting a  
bit from the Qn to the Qn–1 output (see Timing Diagram  
B).  
ꢀunctional Block Diagram  
SINB  
SINB*  
Q3  
Q2  
Q1  
Q0  
D
D
D
D
Q
Q
Q
Q
D
D
D
D
Q
Q
Q
Q
SINA  
SINA*  
SEL  
The MODE input is used to select the conversion mode  
of the device. With the MODE input LOW, or open, the  
device will function as a 4-bit converter. When the mode  
input is driven HIGH, the data on the output will change  
on every eighth clock cycle, thus allowing for an 8-bit  
conversion scheme using two E445’s. When cascaded  
in an 8-bit conversion scheme, the devices will not  
operate at the 2.0 Gb/s data rate of a single device.  
Refer to the applications section of this data sheet for  
more information on cascading the E445.  
SOUT  
SOUT*  
0
1
For lower data rate applications, a V reference voltage  
BB  
MODE  
is supplied for single-ended inputs. When operating at  
clock rates above 500 MHz, differential input signals  
CL/4  
Out  
CL/4*  
CLK  
are recommended. For single-ended inputs, the V pin  
In Out  
Latch  
BB  
R
CLK*  
is tied to the inverting differential input and bypassed  
EN  
via a 0.01 µF capacitor. The V provides the switching  
CL/8  
BB  
Out  
CL/8*  
reference for the input differential amplifier. The V  
can also be used to AC couple an input signal.  
BB  
R
SYNC  
D
Q
D
Upon power-up, the internal flip-flops will attain a random  
state. To synchronize multiple E445’s in a system, the  
master reset must be asserted.  
Q*  
RESET  
Revision 1/ꢀebruary 21, 2001  
www.semtech.com  
1
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