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SK10E151PJT PDF预览

SK10E151PJT

更新时间: 2024-11-08 22:10:15
品牌 Logo 应用领域
商升特 - SEMTECH 触发器锁存器逻辑集成电路
页数 文件大小 规格书
5页 116K
描述
6-Bit D Register

SK10E151PJT 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:QLCC包装说明:PLASTIC, LCC-28
针数:28Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.58
Is Samacsys:N系列:10E
JESD-30 代码:S-PQCC-J28长度:11.505 mm
逻辑集成电路类型:D FLIP-FLOP最大频率@ Nom-Sup:1100000000 Hz
湿度敏感等级:1位数:6
功能数量:1端子数量:28
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC28,.5SQ
封装形状:SQUARE封装形式:CHIP CARRIER
包装方法:TAPE AND REEL峰值回流温度(摄氏度):225
电源:-5.2 V最大电源电流(ICC):78 mA
传播延迟(tpd):0.67 ns认证状态:Not Qualified
座面最大高度:4.57 mm子类别:FF/Latches
表面贴装:YES技术:ECL
温度等级:INDUSTRIAL端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:11.505 mm最小 fmax:1100 MHz
Base Number Matches:1

SK10E151PJT 数据手册

 浏览型号SK10E151PJT的Datasheet PDF文件第2页浏览型号SK10E151PJT的Datasheet PDF文件第3页浏览型号SK10E151PJT的Datasheet PDF文件第4页浏览型号SK10E151PJT的Datasheet PDF文件第5页 
SK10/100E151  
6-Bit D Register  
HIGH-PERꢀORMANCE PRODUCTS  
ꢀeatures  
Description  
• 1100 MHz Toggle Frequency  
• Extended 100E VEE Range of –4.2V to –5.46V  
• Differential Outputs  
• Asynchronous Master Reset  
• Dual Clocks  
The SK10/100E151 offers 6 edge-triggered, high-speed,  
master-slave D-type flip-flops with differential outputs,  
designed for use in new high-performance ECL systems.  
This device is fully compatible with MC10E151 and  
MC100E151. The two external clock signals (CLK1, CLK2)  
are gated through a logical OR operation before use as  
clocking control for the flip-flops. Data is clocked into  
the flip-flops on the rising edge of either CLK1 or CLK2  
(or both). When both CLK1 and CLK2 are at a logic  
LOW, data enters the master and is transferred to the  
slave when either CLK or CLK2 (or both) go HIGH.  
• Internal 75KInput Pull-Down Resistors  
• ESD Protection of >4000V  
• Fully Compatible with MC10E/100E151  
• Specified Over Industrial Temperature Range:  
o
o
–40 C to +85 C  
• Available in 28-Pin PLCC Package  
The MR (Master Reset) signal operates asynchronously  
to make all Q outputs go to a logic LOW.  
PIN Description  
Pin  
D0–D5  
CLK1, CLK2  
MR  
ꢀunction  
ꢀunctional Block Diagram  
Data Inputs  
Clock Inputs  
Q0  
D0  
D1  
D2  
D3  
D4  
D5  
D
D
D
D
D
D
Master Reset  
True Outputs  
Q0*  
R
R
R
R
R
R
Q0–Q5  
Q0*–Q5*  
VCC0  
Q1  
Inverting Outputs  
VCC to Output  
Q1*  
Q2  
Q2*  
Q3  
Q3*  
Q4  
D5  
D4  
D3  
VEE  
D2  
D1  
D0  
26  
27  
28  
1
18  
17  
16  
15  
14  
13  
12  
Q4*  
Q4  
Q4*  
VCC  
Q3*  
Q3  
PLCC  
TOP VIEW  
Q5  
2
Q5*  
3
Q2*  
Q2  
4
CLK1  
CLK2  
MR  
www.semtech.com  
Revision 1/ꢀebruary 13, 2001  
1

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