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SIHFD113-E3 PDF预览

SIHFD113-E3

更新时间： 2024-11-24 19:57:23
品牌 Logo 应用领域
威世 - VISHAY 开关光电二极管晶体管
页数 文件大小 规格书
8页 243K
描述
TRANSISTOR 800 mA, 60 V, N-CHANNEL, Si, SMALL SIGNAL, MOSFET, ROHS COMPLIANT, PLASTIC, HVMDIP-2, FET General Purpose Small Signal

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SIHFD113-E3 技术参数

生命周期：Active零件包装代码：DIP
包装说明：IN-LINE, R-PDIP-T2针数：2
Reach Compliance Code：unknownECCN代码：EAR99
风险等级：5.22外壳连接：DRAIN
配置：SINGLE WITH BUILT-IN DIODE最小漏源击穿电压：60 V
最大漏极电流 (Abs) (ID)：0.8 A最大漏极电流 (ID)：0.8 A
最大漏源导通电阻：0.8 ΩFET 技术：METAL-OXIDE SEMICONDUCTOR
最大反馈电容 (Crss)：25 pFJESD-30 代码：R-PDIP-T2
元件数量：1端子数量：2
工作模式：ENHANCEMENT MODE最高工作温度：150 °C
封装主体材料：PLASTIC/EPOXY封装形状：RECTANGULAR
封装形式：IN-LINE峰值回流温度（摄氏度）：NOT SPECIFIED
极性/信道类型：N-CHANNEL最大功率耗散 (Abs)：1 W
子类别：FET General Purpose Power表面贴装：NO
端子形式：THROUGH-HOLE端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED晶体管应用：SWITCHING
晶体管元件材料：SILICONBase Number Matches：1

SIHFD113-E3 数据手册

 浏览型号SIHFD113-E3的Datasheet PDF文件第2页浏览型号SIHFD113-E3的Datasheet PDF文件第3页浏览型号SIHFD113-E3的Datasheet PDF文件第4页浏览型号SIHFD113-E3的Datasheet PDF文件第5页浏览型号SIHFD113-E3的Datasheet PDF文件第6页浏览型号SIHFD113-E3的Datasheet PDF文件第7页 
IRFD113, SiHFD113  
www.vishay.com  
Vishay Siliconix  
Power MOSFET  
FEATURES  
PRODUCT SUMMARY  
• For Automatic Insertion  
VDS (V)  
DS(on) (Ω)  
Qg (Max.) (nC)  
60  
• Compact Plastic Package  
• End Stackable  
R
VGS = 10 V  
0.8  
7
• Fast Switching  
Q
gs (nC)  
gd (nC)  
2
7
Q
• Low Drive Current  
Configuration  
Single  
• Easily Paralleled  
• Excellent Temperature Stability  
• Compliant to RoHS Directive 2002/95/EC  
D
Note  
* Pb containing terminations are not RoHS compliant, exemptions  
may apply  
HVMDIP  
DESCRIPTION  
G
The HVMDIP technology is the key to Vishay’s advanced  
line of power MOSFET transistors. The efficient geometry  
and unique processing of the HVMDIP design achieves  
very low on-state resistance combined with high  
transconductance and extreme device ruggedness.  
HVMDIPs feature all of the established advantages of  
MOSFETs such as voltage control, very fast switching, ease  
of paralleling, and temperature stability of the electrical  
parameters.  
S
G
S
N-Channel MOSFET  
D
The HVMDIP 4 pin, dual-in-line package brings the  
advantages of HVMDIPs to high volume applications where  
automatic PC board insertion is desireable, such as circuit  
boards for computers, printers, telecommunications  
equipment, and consumer products. Their compatibility with  
automatic insertion equipment, low-profile and end  
stackable features represent the stat-of-the-art in power  
device packaging.  
ORDERING INFORMATION  
Package  
HVMDIP  
IRFD113PbF  
SiHFD113-E3  
Lead (Pb)-free  
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)  
PARAMETER  
SYMBOL  
LIMIT  
UNIT  
Drain-Source Voltagea  
VDS  
60  
20  
V
Gate-Source Voltage  
VGS  
Continuous Drain Current  
Pulsed Drain Currentb  
VGS at 10 V  
TC = 25 °C  
ID  
0.8  
A
IDM  
6.4  
Linear Derating Factor  
0.008  
6.4  
W/°C  
A
Inductive Current, Clamped  
Maximum Power Dissipation  
Operating Junction and Storage Temperature Range  
Soldering Recommendations (Peak Temperature)  
L = 100 μH  
C = 25 °C  
ILM  
PD  
T
1.0  
W
TJ, Tstg  
- 55 to + 150  
300c  
°C  
for 10 s  
Notes  
a. TJ = 25 °C to 150 °C  
b. Repetitive rating; pulse width limited by maximum junction temperature.  
c. 1.6 mm from case.  
S11-2479-Rev. A, 19-Dec-11  
Document Number: 91487  
1
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT  
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000  
12345678

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