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SI5319B-C-GM PDF预览

SI5319B-C-GM

更新时间: 2024-11-19 13:13:31
品牌 Logo 应用领域
芯科 - SILICON 衰减器时钟
页数 文件大小 规格书
16页 252K
描述
Clock Generator, 808MHz, CMOS, 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD, QFN-36

SI5319B-C-GM 技术参数

是否Rohs认证:符合生命周期:Active
零件包装代码:QFN包装说明:HVQCCN, LCC36,.25SQ,20
针数:36Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:1.03Is Samacsys:N
其他特性:IT CAN ALSO OPERATES 2.5V OR 3.3V NON SUPPLYJESD-30 代码:S-XQCC-N36
长度:6 mm端子数量:36
最高工作温度:85 °C最低工作温度:-40 °C
最大输出时钟频率:808 MHz封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装等效代码:LCC36,.25SQ,20
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):NOT SPECIFIED电源:1.8/3.3 V
主时钟/晶体标称频率:710 MHz认证状态:Not Qualified
座面最大高度:0.9 mm子类别:Clock Generators
最大压摆率:243 mA最大供电电压:1.89 V
最小供电电压:1.71 V标称供电电压:1.8 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:6 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

SI5319B-C-GM 数据手册

 浏览型号SI5319B-C-GM的Datasheet PDF文件第2页浏览型号SI5319B-C-GM的Datasheet PDF文件第3页浏览型号SI5319B-C-GM的Datasheet PDF文件第4页浏览型号SI5319B-C-GM的Datasheet PDF文件第5页浏览型号SI5319B-C-GM的Datasheet PDF文件第6页浏览型号SI5319B-C-GM的Datasheet PDF文件第7页 
Si5319  
PRELIMINARY DATA SHEET  
ANY-RATE PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR  
Description  
Features  
The Si5319 is a jitter-attenuating precision M/N clock  
multiplier for applications requiring sub 1 ps jitter  
performance. The Si5319 accepts one clock input ranging  
from 2 kHz to 710 MHz and generates one clock output  
ranging from 2 kHz to 945 MHz and select frequencies to  
1.4 GHz. The Si5319 can also use its crystal oscillator as a  
clock source for frequency synthesis. The device provides  
virtually any frequency translation combination across this  
operating range. The Si5319 input clock frequency and clock  
multiplication ratio are programmable through an I2C or SPI  
interface. The Si5319 is based on Silicon Laboratories' 3rd-  
generation DSPLL® technology, which provides any-rate  
frequency synthesis and jitter attenuation in a highly  
integrated PLL solution that eliminates the need for external  
VCXO and loop filter components. The DSPLL loop  
bandwidth is digitally programmable, providing jitter  
performance optimization at the application level. Operating  
from a single 1.8, 2.5, or 3.3 V supply, the Si5319 is ideal for  
providing clock multiplication and jitter attenuation in high  
performance timing applications.  
Generates any frequency from 2 kHz to 945 MHz  
and select frequencies to 1.4 GHz from an input  
frequency of 2 kHz to 710 MHz  
Ultra-low jitter clock outputs with jitter generation as  
low as 0.3 ps rms (50 kHz–80 MHz)  
Integrated loop filter with selectable loop bandwidth  
(60 Hz to 8.4 kHz)  
Meets OC-192 GR-253-CORE jitter specifications  
Clock or crystal input with manual clock selection  
Clock output selectable signal format  
(LVPECL, LVDS, CML, CMOS)  
Support for ITU G.709 and custom FEC ratios  
(255/238, 255/237, 255/236)  
Supports various frequency translations for  
Synchronous Ethernet  
LOL, LOS alarm outputs  
2
I C or SPI programmable  
On-chip voltage regulator for 1.8 V ±5%, 2.5 or  
Applications  
3.3 V ±10% operation  
SONET/SDH OC-48/STM-16 and OC-192/STM-64  
line cards  
Small size: 6 x 6 mm 36-lead QFN  
Pb-free, ROHS compliant  
GbE/10GbE, 1/2/4/8/10GFC line cards  
ITU G.709 and custom FEC line cards  
Optical modules  
Wireless basestations  
Data converter clocking  
xDSL  
Synchronous Ethernet  
Test and measurement  
Discrete PLL replacement  
Broadcast video  
Xtal or Refclock  
XO  
÷ NC1_LS  
CKOUT  
÷ N32  
®
DSPLL  
N1_HS  
÷ N31  
CKIN  
÷ N2  
VDD (1.8, 2.5, or 3.3 V)  
GND  
Loss of Signal  
Loss of Lock  
Control  
Signal Detect  
I2C/SPI Port  
Xtal/Clock Select  
Device Interrupt  
Rate Select  
Preliminary Rev. 0.3 1/08  
Copyright © 2008 by Silicon Laboratories  
Si5319  
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.  

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