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SI5319C-C-GMR PDF预览

SI5319C-C-GMR

更新时间: 2024-11-19 19:59:15
品牌 Logo 应用领域
芯科 - SILICON 时钟外围集成电路晶体
页数 文件大小 规格书
50页 1931K
描述
Clock Generator, 364MHz, CMOS, 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD, QFN-36

SI5319C-C-GMR 技术参数

是否Rohs认证: 符合生命周期:Active
零件包装代码:QFN包装说明:HVQCCN, LCC36,.25SQ,20
针数:36Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:1.03其他特性:IT CAN ALSO OPERATES 2.5V OR 3.3V NON SUPPLY
JESD-30 代码:S-XQCC-N36长度:6 mm
湿度敏感等级:2端子数量:36
最高工作温度:85 °C最低工作温度:-40 °C
最大输出时钟频率:364 MHz封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装等效代码:LCC36,.25SQ,20
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260电源:1.8/3.3 V
主时钟/晶体标称频率:710 MHz认证状态:Not Qualified
座面最大高度:0.9 mm子类别:Clock Generators
最大压摆率:243 mA最大供电电压:1.89 V
最小供电电压:1.71 V标称供电电压:1.8 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:6 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHERBase Number Matches:1

SI5319C-C-GMR 数据手册

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Si5319  
ANY-FREQUENCY PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR  
Features  
Generates any frequency from 2 kHz to 945 MHz and  
select frequencies to 1.4 GHz from an input frequency of  
2 kHz to 710 MHz  
Ultra-low jitter clock output with jitter generation as low as  
0.3 ps rms (50 kHz–80 MHz)  
Integrated loop filter with selectable loop bandwidth  
(60 Hz to 8.4 kHz)  
Meets OC-192 GR-253-CORE jitter specifications  
Clock or crystal input with manual clock selection  
Selectable clock output signal format  
Support for ITU G.709 and custom OTN FEC ratios (e.g.  
255/238, 255/237, 255/236)  
Supports various frequency translations for Synchronous  
Ethernet  
LOL, LOS alarm outputs  
I2C or SPI programmable  
On-chip voltage regulator for 1.8 V ±5%, 2.5 V ±10% or  
3.3 V ±10% operation  
Small size: 6 x 6 mm 36-lead QFN  
Pb-free, ROHS compliant  
(LVPECL, LVDS, CML, CMOS)  
Applications  
10G/40G/100G OTN line cards  
SONET/SDH OC-48/STM-16 and OC-192/STM-64  
line cards  
GbE/10GbE, 1/2/4/8/10GFC line cards  
ITU G.709 and custom FEC line cards  
Synchronous Ethernet  
Wireless basestations  
Data converter clocking  
DSLAM/MSANs  
Test and measurement  
Broadcast video  
Discrete PLL replacement  
Optical modules  
Description  
The Si5319 is a jitter-attenuating precision M/N clock multiplier for applications requiring sub 1 ps jitter performance. The  
Si5319 accepts one clock input ranging from 2 kHz to 710 MHz and generates one clock output ranging from 2 kHz to 945 MHz  
and select frequencies to 1.4 GHz. The Si5319 can also use its crystal oscillator as a clock source for free-running clock  
generation. The device provides virtually any frequency translation combination across this operating range. The Si5319 input  
clock frequency and clock multiplication ratio are programmable through an I2C or SPI interface. The Si5319 is based on Silicon  
Laboratories' third-generation DSPLL® technology, which provides any-frequency synthesis and jitter attenuation in a highly  
integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is  
digitally programmable, providing jitter performance optimization at the application level. Operating from a single 1.8, 2.5, or  
3.3 V supply, the Si5319 is ideal for providing clock multiplication and jitter attenuation in high performance timing applications.  
Rev. 1.0 12/10  
Copyright © 2010 by Silicon Laboratories  
Si5319  

SI5319C-C-GMR 替代型号

型号 品牌 替代类型 描述 数据表
SI5319C-C-GM SILICON

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Clock Generator, 364MHz, CMOS, 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD, QFN-36

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