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S3053TT PDF预览

S3053TT

更新时间: 2024-01-18 18:42:23
品牌 Logo 应用领域
AMCC ATM异步传输模式电信电信集成电路
页数 文件大小 规格书
10页 95K
描述
Mux/Demux, 1-Func, PQFP52, HEAT SINK, TQFP-52

S3053TT 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:HLQFP,针数:52
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.83JESD-30 代码:S-PQFP-G52
长度:10 mm功能数量:1
端子数量:52最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:HLQFP封装形状:SQUARE
封装形式:FLATPACK, HEAT SINK/SLUG, LOW PROFILE认证状态:Not Qualified
座面最大高度:1.6 mm标称供电电压:3.3 V
表面贴装:YES电信集成电路类型:ATM/SONET/SDH MUX/DEMUX
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
宽度:10 mmBase Number Matches:1

S3053TT 数据手册

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®
DEVICE  
SPECIFICATION  
2.488 GBPS – 2.7 GBPS QUAD MUX WITH FAN OUT BUFFERS  
S3053  
FEATURES  
GENERAL DESCRIPTION  
• Supports 2.488 Gbit/sec – 2.7 Gbit/sec  
data rates  
The S3053 is a high performance quad mux with fan  
out buffers. It is designed to minimize jitter accumu-  
lation by providing a high bandwidth fully differential  
signal path. It can be used to switch OC-48 (with  
FEC) data signals in Dense Wavelength Division  
Multiplexer designs and other high speed serial  
switch designs.  
• Fully differential for minimum  
jitter accumulation  
• TTL select  
• High speed 50source terminated outputs  
• 0.84 W typical power dissipation  
• 3.3 V power supply  
The chip is designed using four 2:1 multiplexers. It  
can be used to fan out and/or multiplex high speed  
clock and data signals. The S3053 is compatible  
with the AMCC clock recovery, MUX/DEMUX and  
Crosspoint Switch products (up to 2.7 GHz). This  
allows signal integrity to be maintained throughout  
the system design.  
• 52 Pin TQFP/TEP  
The primary AC parameter of importance is the de-  
terministic jitter or data eye degradation inserted by  
the crosspoint. The design minimizes jitter accumu-  
lation by using high bandwidth, low skew fully differ-  
ential circuits. This provides for symmetric rise and  
fall delays as well as noise rejection.  
Figure 1. S3053 Block Diagram  
SELA  
OUTB0P  
SELB  
OUTB0N  
INA0P  
0
INA0N  
OUTB1P  
MUX  
A
0
OUTB1N  
MUX  
B
INA1P  
1
INA1N  
1
IND0P  
OUTC0P  
OUTC0N  
0
0
MUX  
C
IND0N  
MUX  
D
1
OUTC1P  
OUTC1N  
IND1P  
1
IND1N  
SELC  
SELD  
1
October 10, 2000 / Revision D  

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