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S3063TT PDF预览

S3063TT

更新时间: 2024-09-23 20:02:07
品牌 Logo 应用领域
AMCC ATM异步传输模式电信电信集成电路
页数 文件大小 规格书
22页 157K
描述
Transmitter, 1-Func, PQFP100, HEAT SINK, TQFP-100

S3063TT 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:HLFQFP,针数:100
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.81应用程序:ATM;SDH;SONET
JESD-30 代码:S-PQFP-G100长度:14 mm
功能数量:1端子数量:100
封装主体材料:PLASTIC/EPOXY封装代码:HLFQFP
封装形状:SQUARE封装形式:FLATPACK, HEAT SINK/SLUG, LOW PROFILE, FINE PITCH
认证状态:Not Qualified座面最大高度:1.6 mm
标称供电电压:3.3 V表面贴装:YES
电信集成电路类型:ATM/SONET/SDH TRANSMITTER端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
宽度:14 mmBase Number Matches:1

S3063TT 数据手册

 浏览型号S3063TT的Datasheet PDF文件第2页浏览型号S3063TT的Datasheet PDF文件第3页浏览型号S3063TT的Datasheet PDF文件第4页浏览型号S3063TT的Datasheet PDF文件第5页浏览型号S3063TT的Datasheet PDF文件第6页浏览型号S3063TT的Datasheet PDF文件第7页 
®
DEVICE  
SPECIFICATION  
SONET/SDH/ATM OC-48 DIFFERENTIAL 16:1 TRANSMITTER  
S3063  
GENERAL DESCRIPTION  
FEATURES  
• Micro-power Bipolar supply  
• Complies with Bellcore, and ITU-T  
specifications  
• On-chip high-frequency PLL for clock  
generation  
• Supports 2.488 Gbps (OC-48)  
• Reference frequency of 155.52 MHz  
• Interface to both LVPECL and LVTTL logic  
• 16-bit Differential LVPECL data path  
• Compact 100 TQFP/TEP package  
• Diagnostic loopback mode  
• Line loopback mode  
The S3063 SONET/SDH MUX chip is a fully integrated  
serialization SONET OC-48 (2.488 Gbps) interface de-  
vice. The chip performs all necessary parallel-to-serial  
functions in conformance with SONET/SDH transmis-  
sion standards. The device is suitable for SONET-  
based ATM applications. Figure 1 shows a typical  
network application.  
On-chip clock synthesis PLL components are con-  
tained in the S3063 MUX chip allowing the use of a  
slower external transmit clock reference. The chip  
can be used with a 155.52 MHz reference clock, in  
support of existing system clocking schemes.  
• Lock detect  
The low jitter LVPECL interface guarantees compli-  
ance with the bit-error rate requirements of the  
Bellcore and ITU-T standards. The S3063 is pack-  
aged in a 100 TQFP/TEP, offering designers a small  
package outline.  
• Low jitter LVPECL interface  
• Internal FIFO to decouple transmit clocks  
• Single 3.3V supply  
• Typical power 1.45 W  
APPLICATIONS  
• SONET/SDH-based transmission systems  
• SONET/SDH modules  
• SONET/SDH test equipment  
• ATM over SONET/SDH  
• DWDM Systems  
• Section repeaters  
• Add Drop Multiplexers (ADM)  
• Broad-band cross-connects  
• Fiber optic terminators  
• Fiber optic test equipment  
Figure 1. System Block Diagram  
16  
16  
S3063  
Tx  
S3064  
OTX  
ORX  
S3056  
OTX  
Rx  
16  
16  
S3064  
Rx  
S3063  
Tx  
S3056  
ORX  
December 6, 1999 / Revision NC  
1

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