PM5317
SPECTRA-9953
Preliminary
SONET/SDH Payload Extractor/Aligner for 9953 Mbit/s
clock synthesis and serializer-
deserializer components.
• Maps SONET/SDH payloads to
FEATURES
system timing, accommodating
plesiochronous timing offsets between
the line and system timing references,
through pointer processing.
• Provides STS-12 cross-connect
capability for grooming traffic at the
ADD and DROP TelecomBus
• Monolithic single channel STS-
192/STM-64 or quad channel STS-
48/STM-16 SONET/SDH Payload
extractor/aligner.
• Designed for use in interface
applications operating at serial
interface speeds of up to OC-192
rates:
• In quad STS-48/STM-16 mode,
supports four duplex 4-bit 622 MHz
LVDS line side interfaces for direct
connection to external clock recovery,
clock synthesis and serializer-
deserializer components.
interface.
• Standard OIF SFI-4 (16 x 622 Mbit/s)
line side interface.
• The entire SONET/SDH transport
overhead is extracted to and inserted
from dedicated pins. Path BIP-8 error
counts are extracted to dedicated pins.
• Frames to the SONET/SDH receive
stream, inserts framing bytes and STS
identification into the transmit stream,
and processes or inserts the transport
overhead.
• Interprets or generates the STS (AU)
pointer bytes (H1, H2, H3), extracts or
inserts the synchronous payload
envelope(s) and processes or inserts
the path overhead.
•
single STS-192c (STM-64/
AU4-64c);
• Each channel provides termination for
SONET Section, Line and Path
overhead or SDH Regenerator
Section, Multiplexer Section and High
Order Path overhead.
• Provides a 16-bit 622 Mbit/s 8B10B
encoded (777.7 MHz) ADD and DROP
serial TelecomBus interface for
grooming a single STS-192/STM-64
stream.
• Provides four 4-bit 622 Mbit/s 8B10B
encoded (777.7 MHz) ADD and DROP
serial TelecomBus interfaces for
grooming four STS-48/STM-16
streams.
•
single STS-192 (STM-64/AU4-
16c/AU4-4c/AU4/AU3) channelized
to STS-1;
•
•
quad STS-48c (STM-16/AU4-16c);
quad STS-48 (STM-16/
AU4-4c/AU4/AU3);
•
pointer processing for STS-1,
STS-3c, STS-12c, STS-24c, STS-
48c, and STS-192c traffic.
• In single STS-192/STM-64 mode,
supports a duplex 16-bit 622 MHz
LVDS line side interface for direct
connection to external clock recovery,
BLOCK DIAGRAM
Receive O/H Clock, Frame
Pulse
Receive Transport Overhead
Receive Section/Line DCC and
Clock
Status
Information
B3E
Transport
Processing Slice x 4
Rx Ring
Control
Port
Rx APS
Sync
Section
Extractor
Trace
Path Processing Slice:
192 x STS-1
Path
Trace
Processor
&
Processor
Bit Error
Monitor
OC-192 Mode:
16 x 622 MHz
LVDS
OC-192 Mode:
16 x 777 MHz LVDS
Rx
Telecom
Aligner
STS-12
XC
8B/10B
Encoder
LVDS
Transmitter
Rx Path O/H
Processor
Rx Line
Interface
PISO
RX Transport
O/H Processor
4 x OC-48 Mode:
4 x 4 x 777 MHz
LVDS
4 x OC-48 Mode:
4 x 4 x 622 MHz
LVDS
SONET/SDH
Alarm
Reporting
Controller
Alarm
Reporting
Path
Trace
Processor
Section
Trace
Processor
OC-192 Mode:
16 x 622 MHz
LVDS
OC-192 Mode:
16 x 777 MHz LVDS
Tx
Tx Pointer
Tx Line
Interface
STS-12
XC
8B/10B
Decoder
LVDS
Receiver
Tx Path O/H
Processor
DRU
Telecom Interpreter
Aligner
Tx Transport
O/H Processor
4 x OC-48 Mode:
4 x 4 x 777 MHz
LVDS
4 x OC-48 Mode:
4 x 4 x 622 MHz
LVDS
Tx Ring
Control Port
JTAG Test
Access Port
Mode
Microprocessor Interface
16-bit
Microprocessor
Bus
Control
and
Status
Transmit
Transport
O/H
Quad 2488
or 9953
Test Data
Information
PMC-2000992 (P2)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
Copyright PMC-Sierra, Inc. 2001
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