PM5333
ARROW 8xFE
Preliminary
8 Channel 10/100 Ethernet over SONET/SDH Mapping Device
• Supports loss-less IEEE 802.3 local
flow-control.
• Supports insertion and extraction of
GFP Client Management Frames
(CMF).
• Supports insertion and extraction of
LCP, NCP and BCP control frames.
FEATURES
• Maps up to eight channels of full-
duplex 10/100M Ethernet into 622
Mbps SONET/SDH.
• Supports multiple encapsulation
protocols for worldwide interoperability
including GFP, LAPS, and flexible
HDLC.
• Performs virtual and contiguous
concatenation according to ITU-T
G.707 and ANSI T1.105.
• Supports selection of STS-1/VC-3
virtual concatenation, VT1.5/VC-12
virtual concatenation or STS-3c on a
per port basis.
• Generates and terminates High-Order
and Low-Order SONET/SDH POH.
• Supports bandwidth provisioning in
arbitrary steps of 1.6 Mbit/s (VT1.5) or
2.2 Mbit/s (VC-12).
• Supports hitless Link Capacity
Adjustment Scheme (LCAS).
• Supports up to 64 ms of differential
delay.
• Provides per port Ethernet Statistics
using 32-bit counters for frames and
40-bit counters for octets to ensure
rollover compliance of 58 minutes as
per IEEE 802.3.
• Supports frame delineation and
generation with configurable IPG,
preamble and CRC.
• Supports transparent transmission of
VLAN tagged Ethernet frames.
• Supports frame sizes of 64 bytes to
9632 bytes.
• Supports programmable frame
truncation from 1518 bytes to 9632
bytes.
SONET/SDH SUBSYSTEM
• Supports High-Order POH processing
and pointer interpretation for STS-1,
STS-3c, AU-3 and AU-4.
• Supports Low-Order POH processing
and pointer interpretation for VT1.5,
TU-12 and TU-3.
• Provides on-chip data and clock
recovery and clock synthesis for
SONET/SDH interfaces.
• Supports TOH and High-Order POH
insertion and extraction.
• Supports programmable depth full-
packet store-and-forward buffers for
burst tolerance and rate adaptation.
• Supports up to 512 Kbytes ingress
buffering per port.
• Supports Low-Order POH insertion
and extraction.
• Supports the following mapping
formats:
•
•
•
C-12/ VC-12/ TU-12/ TUG-2/ TUG-
3/ VC-4/ AU-4/ STM-1.
• Supports 23 Kbytes egress buffering
per port.
C-12/ VC-12/ TU-12/ TUG-2/ VC-3/
AU-3/ STM-1.
ENCAPSULATION
• Supports the following encapsulation
protocols on a per port basis:
ETHERNET SUBSYSTEM
C-3/ VC-3/ TU-3/ TUG-3/ VC-4/ AU-
4/ STM-1.
• Provides integrated IEEE 802.3 com-
pliant media access controllers (MAC).
• Provides IEEE 802.3 compliant
Ethernet management interface
(MDIO).
• Supports interfacing to full duplex
10/100M connections via SMII or SS-
SMII.
•
•
•
ITU-T G.7041 Generic Framing
Procedure (frame-based).
•
•
•
C-3/ VC-3/ AU-3/ STM-1.
C-4/ VC-4/ AU-4/ STM-1.
ITU-T X.86 Link Access Procedure
for SDH (LAPS).
VT1.5 SPE/ VT1.5/ STS-1 SPE/
STS-1.
Flexible HDLC.
•
•
STS-1 SPE/ STS-1.
STS-3c SPE/ STS-3c.
Differential Delay
TOH /
BLOCK DIAGRAM
Buffer
Low-Order
High-Order
Clocks
(DRAM)
POH Extract
POH Extract
8 x 10 / 100
SMII or SS-SMII
1x622 MHz Serial SONET/SDH
or
1x777 MHz Serial TelecomBus
Egress
Packet Buffer
JTAG
Test Access Port
Clock
Generation
SONET/SDH Subsystem
Working
Protect
Rx
LVDS
Low-Order
Path
Processor
and
Mapper/
Demapper
High-Order
SONET/SDH
Time
Slot
Interchange
(TSI)
Virtual
Concatenation
and
LCAS
Engine
Path
Processor
and
Mapper/
Demapper
Ethernet
Subsystem
Encapsulation
Engine
Working
Protect
Tx
LVDS
Ethernet
Management
Interface
16-bit
Microprocessor
Interface
(MDIO)
Ingress
Packet Buffer
(DRAM)
TOH /
High-Order
POH Insert
Low-Order
POH Insert
Working / Protect
Select
PMC-2012677 (p3)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
© Copyright PMC-Sierra, Inc. 2003.
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