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PM5329-FEI PDF预览

PM5329-FEI

更新时间： 2024-11-09 19:48:23
品牌 Logo 应用领域
美国微芯 - MICROCHIP ATM异步传输模式电信电信集成电路
页数 文件大小 规格书
2页 258K
描述
ATM/SONET/SDH Support Circuit, 1-Func, PBGA672

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中文翻译

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PM5329-FEI 技术参数

生命周期：Active包装说明：BGA,
Reach Compliance Code：compliantFactory Lead Time：10 weeks
风险等级：5.79JESD-30 代码：S-PBGA-B672
功能数量：1端子数量：672
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装形状：SQUARE封装形式：GRID ARRAY
标称供电电压：1.2 V表面贴装：YES
电信集成电路类型：ATM/SONET/SDH SUPPORT CIRCUIT端子形式：BALL
端子位置：BOTTOMBase Number Matches：1

PM5329-FEI 数据手册

 浏览型号PM5329-FEI的Datasheet PDF文件第2页 
PM5329 ARROW 24xFE  
24 Channel 10/100 Ethernet Over SONET/SDH  
Mapping Device  
Released Product Brief  
• Supports loss-less IEEE 802.3 local flow-control  
Product Highlights  
• Maps up to 24 channels of full-duplex 10/100M Ethernet into  
• Provides per port Ethernet Statistics using 32-bit counters for  
frames and 40-bit counters for octets to ensure rollover  
compliance of 58 minutes as per IEEE 802.3  
2.488 Gbit/s SONET/SDH  
• Supports multiple encapsulation protocols for worldwide  
interoperability including GFP, LAPS, and flexible HDLC  
• Supports frame delineation and generation with configurable  
IPG, preamble and CRC  
• Performs virtual and contiguous concatenation according to  
ITU-T G.707 and ANSI T1.105  
• Supports transparent transmission of VLAN tagged Ethernet  
frames  
• Supports selection of STS-1/VC-3 virtual concatenation,  
VT1.5/VC-12 virtual concatenation or STS-3c/VC-4 on a per port  
basis  
• Supports frame sizes of 64 bytes to 9632 bytes  
• Supports programmable frame truncation from 1518 bytes to  
9632 bytes  
• Supports STS-48/STM-16 of high-order (STS-1/ VC-3) and STS-  
12/STM-4 of low-order (VT1.5/ VC-12) concatenation  
• Supports programmable depth full-packet store-and-forward  
buffers for burst tolerance and rate adaptation  
• Generates and terminates High-Order and Low-Order  
SONET/SDH POH  
• Supports up to 512 Kbytes ingress buffering per port  
• Supports 23 Kbytes egress buffering per port  
• Supports bandwidth provisioning in arbitrary steps of 1.6 Mbit/s  
(VT1.5) or 2.2 Mbit/s (VC-12)  
Encapsulation  
• Supports the following encapsulation protocols on a per port  
basis:  
• Supports hitless Link Capacity Adjustment Scheme (LCAS)  
• Supports up to 64 ms of differential delay  
•
•
•
ITU-T G.7041 Generic Framing Procedure (frame-based)  
ITU-T X.86 Link Access Procedure for SDH (LAPS)  
Flexible HDLC  
Ethernet Subsystem  
• Provides integrated IEEE 802.3 com-pliant media access  
controllers (MAC)  
• Supports insertion and extraction of GFP Client Management  
Frames (CMF)  
• Provides IEEE 802.3 compliant Ethernet management interface  
(MDIO)  
• Supports insertion and extraction of LCP, NCP and BCP control  
frames  
• Supports interfacing to full duplex 10/100M connections via SMII  
or SS-SMII  
Block Diagram  
Differential  
Delay Buffer  
(DDR SDRAM)  
TOH /  
High-Order  
POH Extract  
Low-Order  
POH Extract  
Clocks  
24 x 10 / 100  
SMII or SS-SMII  
4x622 MHz Serial SONET/SDH  
Egress  
Packet Buffer  
JTAG  
Test Access Port  
Clock  
Generation  
or  
4x777 MHz Serial TelecomBus  
or  
1x2.488 GHz Serial SONET/SDH  
SONET/SDH Subsystem  
Working  
Protect  
Rx  
LVDS  
Low-Order  
Path  
Processor  
and  
Mapper/  
Demapper  
High-Order  
Path  
Processor  
and  
Mapper/  
Demapper  
SONET/SDH  
Virtual  
Concatenation  
and  
Time  
Slot  
Ethernet  
Subsystem  
Encapsulation  
Engine  
Interchange  
(TSI)  
LCAS  
Engine  
Working  
Protect  
Tx  
LVDS  
Ethernet  
Management  
Interface  
16-bit  
Microprocessor  
Interface  
(MDIO)  
Ingress Packet  
Buffer  
(DDR SDRAM)  
TOH /  
High-Order  
POH Insert  
Low-Order  
POH Insert  
Working / Protect  
Select  
PMC-2012675, Issue 6  
© Copyright PMC-Sierra, Inc. 2004  
All rights reserved. Proprietary and Confidential to PMC-Sierra, Inc. and for its customers’ internal use.  
12

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